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cy7c66013c, cy7c66113c full speed usb (12 mbps) peripheral controller with integrated hub cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-08024 rev. *g revised march 1, 2011 full speed usb (12 mbps) peripheral controller with integrated hub features full speed usb peripheral micr ocontroller with an integrated usb hub ? well suited for usb compound devices such as a keyboard hub function 8-bit usb optimized microcontroller ? harvard architecture ? 6 mhz external clock source ? 12 mhz internal cpu clock ? 48 mhz internal hub clock internal memory ? 256 bytes of ram ? 8 kb of prom integrated master and slave i 2 c compatible controller (100 khz) enabled through general purpose i/o (gpio) pins hardware assisted parallel inte rface (hapi) for data transfer to external devices i/o ports ? three gpio ports (port 0 to 2) capable of sinking 8 ma per pin (typical) ? an additional gpio port (port 3) capable of sinking 12 ma per pin (typical) for high current requirements: leds ? higher current drive achievable by connecting multiple gpio pins together to drive a common output ? each gpio port is configured as inputs with internal pull ups or open drain outputs or traditional cmos outputs ? a digital to analog conversion (dac) port with programmable current sink outputs is available on the cy7c66113c device ? maskable interrupts on all i/o pins 12-bit free running timer with one microsecond clock ticks watchdog timer (wdt) internal power on reset (por) usb specification compliance ? conforms to usb specification, version 1.1 ? conforms to usb hid spec ification, version 1.1 ? supports one or two device addresses with up to five user configured endpoints ? up to two 8-byte control endpoints ? up to four 8-byte data endpoints ? up to two 32-byte data endpoints ? integrated usb transceivers ? supports four downstream usb ports ? gpio pins provide individual power control outputs for each downstream usb port ? gpio pins provide individual port over current inputs for each downstream usb port improved output drivers to redu ce electromagnetic interference (emi) operating voltage from 4.0 v?5.5 v dc operating temperature from 0 ? c?70 ? c cy7c66013c available in 48-pin ssop (-pvxc) packages cy7c66113c available in 56-pin qfn or 56-pin ssop (-pvxc) packages industry standard programmer support functional overview the cy7c66013c and cy7c66113c are compound devices with a full speed usb microcontroller in combination with a usb hub. each device is suited for combination peripheral functions with hubs such as a keyboard hub function. the 8-bit one time programmable microcontroller with a 12 mbps usb hub supports as many as four downstream ports. gpio the cy7c66013c features 29 gpio pins to support usb and other applications. the i/o pins are grouped into four ports (p0[7:0], p1[7:0], p2[7:0], p3[4:0]) where each port is configured as inputs with internal pull ups, open drain outputs, or traditional cmos outputs. ports 0 to 2 are ra ted at 8 ma per pin (typical) sink current. port 3 pins are rated at 12 ma per pin (typical) sink current, which allows these pins to drive leds. multiple gpio pins are connected together to drive a single output for more drive current capacity. additionally, each i/o pin is used to generate a gpio interrupt to the microcontroller. all of the gpio interrupts all share the same ?gpio? interrupt vector. the cy7c66113c has 31 gpio pins (p0[7:0], p1[7:0], p2[7:0], p3[6:0]). dac the cy7c66113c has an additional port p4[7:0] that features an additional eight programmable sink current i/o pins (dac). every dac pin includes an integrated 14 k ? pull up resistor. when a ?1? is written to a dac i/ o pin, the output current sink is disabled and the output pin is driven high by the internal pull up resistor. when a ?0? is written to a dac i/o pin, the internal pull up is disabled and the output pin provides the programmed amount of sink current. a dac i/o pin is used as an input with an internal pull up by writing a ?1? to the pin. the sink current for each dac i/o pin is individually programmed to one of sixteen values using dedicated isink registers. dac bits dac[1:0] is used as high curr ent outputs with a programmable sink current range of 3.2 to 16 ma (typical). dac bits dac[7:2] have a programmable current sink range of 0.2 to 1.0 ma (typical). multiple dac pins ar e connected together to drive a single output that requires more sink current capacity. each i/o pin is used to generate a dac interrupt to the microcontroller. also, the interrupt polarity for each dac i/o pin is individually programmable. [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 2 of 61 clock the microcontroller uses an external 6 mhz crystal and an internal oscillator to provide a reference to an internal pll based clock generator. this technology a llows the customer application to use an inexpensive 6 mhz fundamental crystal that reduces the clock related noise emissions (emi). a pll clock generator provides the 6, 12, and 48 mhz clock signals for distribution within the microcontroller. memory the cy7c66013c and cy7c66113c have 8 kb of prom. power on reset, watchdog, and free running timer these parts include por logic, a wdt, and a 12-bit free-running timer. the por logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at prom address 0x0000. the wdt is used to ensure that the microcontroller recovers after a period of inactivity. the firmware may become inactive for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs. i 2 c and hapi interface the microcontroller communicates with external electronics through the gpio pins. an i 2 c compatible interface accommodates a 100 khz serial link with an external device. there is also a hapi to transfer data to an external device. timer the free-running 12-bit timer clocked at 1 mhz provides two interrupt sources, 128 ? s and 1.024 ms. the timer is used to measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is complete. the difference between the two readings indicates the duration of the event in microsecond s. the upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits. a read fr om the upper four bits actually reads data from the internal register, instead of the timer. this feature eliminates the need for firmware to try to compensate if the upper four bits increment i mmediately after the lower eight bits are read. interrupts the microcontroller supports eleven maskable interrupts in the vectored interrupt controller. interrupt sources include the 128 ? s (bit 6) and 1.024 ms (bit 9) out puts from the free-running timer, five usb endpoints, the usb hub, the dac port, the gpio ports, and the i 2 c compatible master mode interface. the timer bits cause an interrupt (if enabled) when the bit toggles from low ?0? to high ?1.? the usb endpoints interrupt after the usb host has written data to the endpoint fi fo or after the usb controller sends a packet to the usb host. the dac ports have an additional level of masking that allows the user to select which dac inputs causes a dac interrupt. the gpio ports also have a level of masking to select which gpio inputs causes a gpio interrupt. for additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the dac port. input transition polarity is programmed for each gpio port as part of the port configuration. the interrupt polarity can be rising edge (?0? to ?1?) or falling edge (?1? to ?0?). usb the cy7c66013c and cy7c66113c include an integrated usb serial interface engine (sie) that supports the integrated peripherals and the hub controller function. the hardware supports up to two usb device addresses with one device address for the hub (two endpoints) and a device address for a compound device (three endpoints). the sie allows the usb host to communicate with the hub and func tions integrated into the microcontroller. the part includes a 1:4 hub repeater with one upstream port and four downstream ports. the usb hub allows power management control of the downstream ports by using gpio pins assigned by the user firmware. the user has the option of ganging the downstream ports together with a single pair of power management pins, or providing power management for each port with fo ur pairs of power management pins. [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 3 of 61 interrupt controller prom 12-bit timer reset watchdog timer repeater power-on sclk i 2 c usb transceiver usb transceiver usb transceiver gpio port 1 gpio port 0 p0[0] p0[7] p1[0] p1[7] sdata d+[3] d?[3] d+[2] d?[2] 8-bit bus external 6 mhz crystal ram usb sie usb transceiver d+[4] d?[4] usb transceiver d+[0] d?[0] d+[1] d?[1] upstream usb port downstream usb ports gpio port 3 p3[0] p3[4] dac port dac[0] dac[7] high current outputs cy7c66113c only 256 byte 8 kb clock 6 mhz 12 mhz 8-bit cpu *i 2 c-compatible interface enabled by firmware through power management under firmware control using gpio pins interface gpio port 3 p3[5] p3[6] additional outputs high current pll 12 mhz 48 mhz divider gpio/ port 2 p2[0:1,7] p2[3]; data_ready p2[4]; stb p2[5]; oe p2[6]; cs p2[2]; latch_empty hapi p2[1:0] or p1[1:0] logic block diagram [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 4 of 61 contents pin configurations ........................................................... 5 product summary tables ................................................ 9 pin assignments .......................................................... 9 i/o register summary ................................................. 9 instruction set summary ........................................... 11 programming model ....................................................... 12 14-bit program counter (pc) .................................... 12 8-bit accumulator (a ) ................................................. 13 8-bit temporary register (x) ..................................... 13 8-bit program stack pointer (p sp) ............................ 13 8-bit data stack pointer (dsp) .................................. 13 address modes ......................................................... 14 clocking .......................................................................... 14 reset ................................................................................ 15 power on reset ................... ...................................... 15 watchdog reset ....... .............. .............. .............. ....... 15 suspend mode ................................................................ 16 general purpose i/o (gpio) ports ................................ 16 gpio configuration port ........................................... 18 gpio interrupt enable ports ..................................... 19 dac port .......................................................................... 20 dac isink registers .................................................. 21 dac port interrupts ................................................... 21 12-bit free-running timer ..... ........................................ 22 i 2 c and hapi configuration register ........................... 23 i 2 c compatible controller .............................................. 23 hardware assisted parallel interface (hapi) ............... 26 processor status and control register ....................... 27 interrupts ......................................................................... 28 interrupt vectors ........................................................ 29 interrupt latency ....................................................... 30 usb bus reset interrupt ........ ................................... 30 timer interrupt ........................................................... 30 usb endpoint interrupts ............................................ 30 usb hub interrupt ..................................................... 30 dac interrupt ............................................................ 31 gpio and hapi interrupt ........ .............. .............. ....... 31 i 2 c interrupt ............................................................... 32 usb overview ................................................................. 32 usb serial interface engine .. .................................... 32 usb enumeration ...................................................... 32 usb hub .......................................................................... 33 connecting and disconnecting a usb device .......... 33 enabling and disabling a usb device ...................... 34 hub downstream ports status and control .............. 35 downstream port suspend an d resume .... .............. 36 usb upstream port status and control .................... 38 usb sie operation ......................................................... 39 usb device addresses ............................................. 39 usb device endpoints .............................................. 39 usb control endpoint mode registers ..................... 39 usb non control endpoint mode registers ............. 41 usb endpoint counter regist ers .............................. 41 endpoint mode and count registers update and locking mechanism .......................................................... 42 usb mode tables ........................................................... 44 register summary .......................................................... 48 sample schematic .......................................................... 50 absolute maximum ratings .......................................... 51 electrical characteristics ............................................... 51 switching characteristics .............................................. 52 ordering information ...................................................... 55 ordering code definitions ..... .................................... 55 package diagrams .......................................................... 56 quad flat package no leads (qfn) package design notes ................................................................... 58 acronyms ........................................................................ 59 document conventions ................................................. 59 units of measure ....................................................... 59 document history page ................................................. 60 sales, solutions, and legal information ...................... 61 worldwide sales and design s upport ......... .............. 61 products .................................................................... 61 psoc solutions ......................................................... 61 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 5 of 61 pin configurations figure 1. cy7c66013c 48-pin ssop and cy7c66113c 56-pin ssop 1 2 3 4 5 6 7 9 11 12 13 14 15 16 18 17 xtalin 10 8 19 20 39 38 37 41 40 43 42 45 44 47 46 49 48 51 50 53 52 54 56 55 21 22 23 24 25 26 28 27 29 31 30 33 32 35 34 36 v cc p1[1] p1[0] p1[2] p1[4] p1[6] p3[0] d?[3] v ref p1[3] p1[5] p1[7] p3[1] d+[0] d?[0] p3[3] gnd p3[5] d+[1] d?[1] p2[1] d+[2] d?[2] p2[3] p2[5] p2[7] dac[7] p0[7] p0[5] p0[3] p0[1] dac[5] dac[3] dac[1] xtalout d+[3] p3[2] p3[4] d?[4] d+[4] p3[6] p2[0] p2[2] gnd p2[4] p2[6] dac[0] v pp p0[0] p0[2] p0[4] p0[6] dac[2] dac[4] dac[6] cy7c66113c cy7c66013c 1 2 3 4 5 6 7 9 11 12 13 14 15 16 18 17 xtalin 10 8 19 20 31 30 29 33 32 35 34 37 36 39 38 41 40 43 42 45 44 46 48 47 21 22 23 24 25 27 26 28 v cc p1[1] p1[0] p1[2] p1[4] p1[6] p3[0] d?[3] v ref p1[3] p1[5] p1[7] p3[1] d+[0] d?[0] p3[3] gnd d+[1] d?[1] p2[1] d+[2] d?[2] p2[3] p2[5] p2[7] gnd p0[7] p0[5] p0[3] p0[1] xtalout d+[3] p3[2] gnd p3[4] d?[4] d+[4] p2[0] p2[2] gnd p2[4] p2[6] v pp p0[0] p0[2] p0[4] p0[6] top view [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 6 of 61 figure 2. cy7c66113c 56-pin qfn 28 27 26 25 24 23 22 21 20 19 18 17 16 15 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 p3[0] d?[3] d+[3] p3[2] p3[4] d?[4] d+[4] p3[6] p2[0] p2[2] gnd p2[4] p2[6] dac[0] d-[0] p3[3] gnd p3[5] d+[1] d?[1] p2[1] d+[2] d?[2] p2[3] p2[5] p2[7] dac[7] p0[7] p1[6] p1[4] p1[2] p1[0] p1[1] vcc xtalout xtalin vref p1[3] p1[5] p1[7] p3[1] d+[0] vpp p0[0] p0[2] p0[4] p0[6] dac[2] dac[4] dac[6] dac[1] dac[3] dac[5] p0[1] p0[3] p0[5] cy7c66113c 56-pin qfn [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 7 of 61 figure 3. cy7c66113c die cypress logo pin 1 pin 60 pin 15 pin 30 pin 45 (0,0) (3398, 4194) die step: 3398 x 4194 microns die size: 3322 x 4129 microns die thickness: 14 mils = 355.6 microns pad size: 80 x 80 microns [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 8 of 61 table 1. pad coordinates in microns (0,0) to bond pad centers pad no. pin name x y pad # pin name x y 1 xtalout 1274.2 3588.8 37 dac6 2000.6 210.6 2 xtalin 1132.8 3588.8 38 dac4 2103.6 210.6 3 vref 889.85 3588.8 39 dac2 2206.6 210.6 4 port11b 684.65 3588.8 40 port06 2308.4 210.6 5 port13 581.65 3588.8 41 port04 2411.4 210.6 6 port15 478.65 3588.8 42 port02 2514.4 210.6 7 vss 375.65 3588.8 43 port00 2617.4 210.6 8 port17 0 3408.35 44 vpp 2992.4 25.4 9 port31 0 3162.05 45 dac0 2992.4 151.75 10 du+ 0 3060.55 46 port26 2992.4 306.15 11 du? 0 2752.4 47 dd+6 2992.4 407.65 12 port33 0 2650.95 48 dd?6 2992.4 715.75 13 vss 0 2474.6 49 port24 2992.4 817.25 14 port35 0 2368.45 50 vss 2992.4 923.4 15 dd+1 0 2266.95 51 port22 2992.4 1086.75 16 dd?1 0 1958.85 52 dd+5 2992.4 1188.25 17 port37 0 1857.35 53 dd?5 2992.4 1496.35 18 vref 0 1680.4 54 port20 2992.4 1597.85 19 port21 0 1567.4 55 vref 2992.4 1710.8 20 dd+2 0 1465.95 56 port36 2992.4 1874.75 21 dd?2 0 1157.85 57 dd+4 2992.4 1976.25 22 port23 0 1056.35 58 dd?4 2992.4 2284.35 23 vss 0 880 59 port34 2992.4 2385.85 24 port25 0 773.85 60 vss 2992.4 2492 25 dd+7 0 672.35 61 port32 2992.4 2655.35 26 dd?7 0 364.25 62 dd+3 2992.4 2756.85 27 port27 0 262.75 63 dd?3 2992.4 3064.95 28 dac7 0 100.75 64 port30 2992.4 3166.45 29 vss 0 0 65 port16 2992.4 3412.25 30 port07 375.2 210.6 66 port14 2634.2 3588.8 31 port05 478.2 210.6 67 port12 2531.2 3588.8 32 port03 581.2 210.6 68 port10 2428.2 3588.8 33 port01 684.2 210.6 69 port11 2325.2 3588.8 34 dac5 788.4 210.6 70 vcc 2221.75 3588.8 35 dac3 891.4 210.6 71 padopt 2121.75 3588.8 36 dac1 994.4 210.6 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 9 of 61 product summary tables pin assignments i/o register summary i/o registers are accessed via the i/o read (iord) and i/o write (iowr, iowx) instructions. iord reads data from the selected p ort into the accumulator. iowr performs the reve rse; it writes data from the accumulator to the selected port. indexed i/o write (i owx) adds the contents of x to the address in the instruction to form the port address and writes data from the accumulator to the s pecified port. specifying address 0 such as iowx 0h indicates the i/o register is selected solely by the contents of x. all undefined registers are reserved. it is important not to write to reserved registers as this may cause an undefined operati on or increased current consumption during operatio n. when writing to register s with reserved bits, the reserved bits must be written with ?0.? table 2. pin assignments name i/o 48-pin 56-pin qfn 56-pin ssop description d+[0], d?[0] i/o 8, 9 56, 1 8, 9 upstream port, usb differential data. d+[1], d?[1] i/o 12, 13 5, 6 13, 14 downstream port 1, usb differential data. d+[2], d?[2] i/o 15, 16 8, 9 16, 17 downstream port 2, usb differential data. d+[3], d?[3] i/o 40, 41 40, 41 48, 49 downstream port 3, usb differential data. d+[4], d?[4] i/o 35, 36 36, 37 44, 45 downstream port 4, usb differential data. p0[7:0] i/o 21, 25, 22, 26, 23, 27, 24, 28 14, 15, 16, 17, 24, 25, 26, 27 22, 32, 23, 33, 24, 34, 25, 35 gpio port 0. p1[7:0] i/o 6, 43, 5, 44, 4, 45, 47, 46 52, 53, 54, 43, 44, 45, 46, 47 6, 51, 5, 52, 4, 53, 55, 54 gpio port 1. p2[7:0] i/o 19, 30, 18, 31, 17, 33, 14, 34 7, 10, 11, 12, 30, 31, 33, 34 20, 38, 19, 39, 18, 41, 15, 42 gpio port 2. p3[6:0] i/o 37, 10, 39, 7, 42 55, 2, 4, 35, 38, 39, 42, 43, 12, 46, 10, 47, 7, 50 gpio port 3, capable of sinking 12 ma (typical). dac[7:0] i/o n/a 13, 18, 19, 20, 21, 22, 23, 29 21, 29, 26, 30, 27, 31, 28, 37 digital to analog converter (dac) port with programmable current sink outputs. dac[1:0] offer a programmable range of 3.2 to 16 ma typical. dac[7:2] have a programmable sink current range of 0.2 to 1.0 ma typical. xtal in in 2 50 2 6 mhz crystal or external clock input. xtal out out 1 49 1 6 mhz crystal out. v pp 29 28 36 programming voltage supply, tie to ground during normal operation. v cc 48 48 56 voltage supply. gnd 11, 20, 32, 38 3, 32 11, 40 ground. v ref in 3 51 3 external 3.3 v supply voltage for the differential data output buffers and the d+ pull up. table 3. i/o register summary register name i/o address read/write function page port 0 data 0x00 r/w gpio port 0 data 16 port 1 data 0x01 r/w gpio port 1 data 17 port 2 data 0x02 r/w gpio port 2 data 17 port 3 data 0x03 r/w gpio port 3 data 17 port 0 interrupt enable 0x04 w interrupt enable for pins in port 0 19 port 1 interrupt enable 0x05 w interrupt enable for pins in port 1 19 port 2 interrupt enable 0x06 w interrupt enable for pins in port 2 19 port 3 interrupt enable 0x07 w interrupt enable for pins in port 3 19 gpio configuration 0x08 r/w gpio port configurations 18 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 10 of 61 hapi and i 2 c configuration 0x09 r/w hapi width and i 2 c position configuration 23 usb device address a 0x10 r/w usb device address a 39 ep a0 counter register 0x11 r/w usb address a, endpoint 0 counter 41 ep a0 mode register 0x12 r/w usb addr ess a, endpoint 0 configuration 40 ep a1 counter register 0x13 r/w usb address a, endpoint 1 counter 41 ep a1 mode register 0x14 r/w usb addr ess a, endpoint 1 configuration 41 ep a2 counter register 0x15 r/w usb address a, endpoint 2 counter 41 ep a2 mode register 0x16 r/w usb addr ess a, endpoint 2 configuration 41 usb status & control 0x1f r/w usb upstream port traffic status and control 38 global interrupt enable 0x20 r/w global interrupt enable 28 endpoint interrupt enable 0x21 r/w usb endpoint interrupt enables 28 interrupt vector 0x23 r pending interrupt vector read/clear 30 timer (lsb) 0x24 r lower 8 bits of free-running timer (1 mhz) 22 timer (msb) 0x25 r upper 4 bits of free-running timer 22 wdt clear 0x26 w watchdog timer clear 15 i 2 c control & status 0x28 r/w i 2 c status and control 24 i 2 c data 0x29 r/w i 2 c data 24 dac data 0x30 r/w dac data 20 dac interrupt enable 0x31 w interrupt enable for each dac pin 21 dac interrupt polarity 0x32 w interrupt polarity for each dac pin 21 dac isink 0x38-0x3f w input sink current control for each dac pin 21 usb device address b 0x40 r/w usb device ad dress b (not used in 5-endpoint mode) 39 ep b0 counter register 0x41 r/w usb address b, endpoint 0 counter 41 ep b0 mode register 0x42 r/w usb addre ss b, endpoint 0 configuration, or usb address a, endpoint 3 in 5-endpoint mode 40 ep b1 counter register 0x43 r/w usb address b, endpoint 1 counter 41 ep b1 mode register 0x44 r/w usb addre ss b, endpoint 1 configuration, or usb address a, endpoint 4 in 5-endpoint mode 41 hub port connect status 0x48 r/w hub downstream port connect status 33 hub port enable 0x49 r/w hub downstream ports enable 34 hub port speed 0x4a r/w hub downstream ports speed 34 hub port control (ports [4:1]) 0x4b r/w hub downstream ports control 35 hub port suspend 0x4d r/w hub downstream port suspend control 36 hub port resume status 0x4e r hub downstream ports resume status 37 hub ports se0 status 0x4f r hub downstream ports se0 status 36 hub ports data 0x50 r hub downstream ports differential data 36 hub downstream force low 0x51 r/w hub downstream ports force low 35 processor status & control 0xff r/w microprocessor status and control register 27 table 3. i/o register summary (continued) register name i/o address read/write function page [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 11 of 61 instruction set summary refer to the cyasm assembler user?s guide for more details. table 4. instruction set summary mnemonic operand opcode cycles mnemonic operand opcode cycles halt 00 7 nop 20 4 add a,expr data 01 4 inc a acc 21 4 add a,[expr] direct 02 6 inc x x 22 4 add a,[x+expr] index 03 7 inc [expr] direct 23 7 adc a,expr data 04 4 inc [x+expr] index 24 8 adc a,[expr] direct 05 6 dec a acc 25 4 adc a,[x+expr] index 06 7 dec x x 26 4 sub a,expr data 07 4 dec [expr] direct 27 7 sub a,[expr] direct 08 6 dec [x+expr] index 28 8 sub a,[x+expr] index 09 7 iord expr address 29 5 sbb a,expr data 0a 4 iowr expr address 2a 5 sbb a,[expr] direct 0b 6 pop a 2b 4 sbb a,[x+expr] index 0c 7 pop x 2c 4 or a,expr data 0d 4 push a 2d 5 or a,[expr] direct 0e 6 push x 2e 5 or a,[x+expr] index 0f 7 swap a,x 2f 5 and a,expr data 10 4 swap a,dsp 30 5 and a,[expr] direct 11 6 mov [expr],a direct 31 5 and a,[x+expr] index 12 7 mov [x+expr],a index 32 6 xor a,expr data 13 4 or [expr],a direct 33 7 xor a,[expr] direct 14 6 or [x+expr],a index 34 8 xor a,[x+expr] index 15 7 and [expr],a direct 35 7 cmp a,expr data 16 5 and [x+expr],a index 36 8 cmp a,[expr] direct 17 7 xor [expr],a direct 37 7 cmp a,[x+expr] index 18 8 xor [x+expr],a index 38 8 mov a,expr data 19 4 iowx [x+expr] index 39 6 mov a,[expr] direct 1a 5 cpl 3a 4 mov a,[x+expr] index 1b 6 asl 3b 4 mov x,expr data 1c 4 asr 3c 4 mov x,[expr] direct 1d 5 rlc 3d 4 reserved 1e rrc 3e 4 xpage 1f 4 ret 3f 8 mov a,x 40 4 di 70 4 mov x,a 41 4 ei 72 4 mov psp,a 60 4 reti 73 8 call addr 50-5f 10 jc addr c0-cf 5 jmp addr 80-8f 5 jnc addr d0-df 5 call addr 90-9f 10 jacc addr e0-ef 7 jz addr a0-af 5 index addr f0-ff 14 jnz addr b0-bf 5 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 12 of 61 programming model 14-bit program counter (pc) the 14-bit pc allows access to up to 8 kb of prom available with the cy7c66x13c architecture. the top 32 bytes of the rom in the 8k part are reserved for testing purposes. the program counter is cleared during reset, such that the fi rst instruction executed after a reset is at address 0x0000h. typically, this is a jump instruction to a reset handler that initializes the application (see interrupt vectors on page 29 ). the lower eight bits of the program counter are incremented as instructions are loaded and execut ed. the upper six bits of the program counter are incremented by executing an xpage instruction. the last instru ction executed within a 256-byte ?page? of sequential code should be an xpage instruction. the assembler directive ?xpageon? c auses the assembler to insert xpage instructions automatically. because instructions are either one or two bytes long, the assembler may occasionally need to insert a nop followed by an xpage to execute correctly. the address of the next instruction to be executed, the carry flag, and the zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a call instruction. the program counter, carry flag, and zero flag are restored from the program stack during a reti instruction. only the program counter is restored during a ret instruction. the program counter is not access ed directly by the firmware. the program stack is examined by reading sram from location 0x00 and up. program memory organization table 5. program memory space with interrupt vector table after reset address 14-bit pc 0x0000 program execution begins here after a reset 0x0002 usb bus reset interrupt vector 0x0004 128 ? s timer interrupt vector 0x0006 1.024 ms timer interrupt vector 0x0008 usb address a endpoint 0 interrupt vector 0x000a usb address a endpoint 1 interrupt vector 0x000c usb address a endpoint 2 interrupt vector 0x000e usb address b endpoint 0 interrupt vector 0x0010 usb address b endpoint 1 interrupt vector 0x0012 hub interrupt vector 0x0014 dac interrupt vector 0x0016 gpio/hapi interrupt vector 0x0018 i 2 c interrupt vector 0x001a program memory begins here 0x1fdf 8 kb (-32) prom ends here. [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 13 of 61 8-bit accumulator (a) the accumulator is the general purpose register for the microcontroller. 8-bit temporary register (x) the ?x? register is available to the firmware for temporary storage of intermediate results. the microcontroller performs indexed operations based on the value in x. refer to the section, indexed on page 14 for additional information. 8-bit program stack pointer (psp) during a reset, the program stack pointer (psp) is set to 0x00 and ?grows? upward from this address. the psp may be set by firmware, using the mov psp,a instruction. the psp supports interrupt service under hardwar e control and call, ret, and reti instructions under firmw are control. the psp is not readable by the firmware. during an interrupt acknowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as two bytes of data memory. the first byte is stored in the memory addressed by the psp, then the psp is incremented. the second byte is stored in memory addressed by the psp, and the psp is incremented again. the overall ef fect is to st ore the program counter and flags on the program ?stack? and increment the psp by two. the return from interrupt (reti) instruction decrements the psp, then restores the second byte from memory addressed by the psp. the psp is decremented again and the first byte is restored from memory addressed by the psp. after the program counter and flags are restored fr om stack, the interrupts are enabled. the overall effect is to restore the program counter and flags from the program stack, decrement the psp by two, and re-enable interrupts. the call subroutine (call) inst ruction stores the program counter and flags on the program stack and increments the psp by two. the return from subroutine (r et) instruction restores the program counter but not the fl ags from the program stack and decrements the psp by two. data memory organization the cy7c66x13c microcontrollers provide 256 bytes of data ram. normally, the sram is partitioned into four areas: program stack, user variables, data stack, and usb endpoint fifos. the following is one example of where the program stack, data stack, and user variables areas are located. 8-bit data stack pointer (dsp) the data stack pointer (dsp) supports push and pop instructions that use the data stack for temporary storage. a push instruction pre-decrements the dsp, then writes data to the memory location addressed by the dsp. a pop instruction reads data from the memory location addressed by the dsp, then post-increments the dsp. during a reset, the dsp is reset to 0x00. a push instruction when dsp equals 0x00 writes data at the top of the data ram (address 0xff). this writes da ta to the memory area reserved for usb endpoint fifos. therefore, the dsp should be indexed at an appropriate memory location that does not compromise the program stack, user defined me mory (variables), or the usb endpoint fifos. for usb applications, the firmware should set the dsp to an appropriate location to avoid a memory conflict with ram dedicated to usb fifos. the me mory requirements for the usb endpoints are described in usb device endpoints on page 39 . example assembly instructions to do this with two device addresses (fifos begin at 0xd8) are shown: mov a,20h; move 20 hex into accumulator (must be d8h or less) swap a,dsp; swap accumulato r value into dsp register. table 6. sram areas after reset address 8-bit dsp 8-bit psp 0x00 program stack growth (move dsp [1] ) 8-bit dsp user selected data stack growth user variables usb fifo space for up to tw o addresses and five endpoints [2] 0xff notes 1. refer to 8-bit data stack pointer (dsp) for a description of dsp. 2. endpoint sizes are fixed by the endpoint size bit (i/o register 0x1f, bit 7), see ta b l e 4 7 . [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 14 of 61 address modes the cy7c66013c and cy7c66113c microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. data (immediate) ?data? address mode refers to a da ta operand that is actually a constant encoded in the instruction. as an example, consider the instruction that loads a with the constant 0xd8: mov a, 0d8h. this instruction requires two bytes of code where the first byte identifies the ?mov a? instruction with a data operand as the second byte. the second byte of the instruction is the constant ?0xd8?. a constant may be referred to by name if a prior ?equ? statement assigns the constant value to the name. for example, the following code is equivalent to the example described earlier: dspinit: equ 0d8h mov a, dspinit. direct ?direct? address mode is used when the data operand is a variable stored in sram. in that case, the one byte address of the variable is encoded in t he instruction. as an example, consider an instruction that loads a with the contents of memory address location 0x10: mov a, [10h]. normally, variable names are assigned to variable addresses using ?equ? statements to improve the readability of the assembler source code. as an example, the following code is equivalent to the example described earlier: buttons: equ 10h mov a, [buttons]. indexed ?indexed? address mode allows the firmware to manipulate arrays of data stored in sram. the address of the data operand is the sum of a constant encoded in the instruction and the contents of the ?x? register. norma lly, the constant is the ?base? address of an array of data and the x register contains an index that indicates which element of the array is actually addressed: array: equ 10h mov x, 3 mov a, [x+array]. this has the effect of loading a with the fourth element of the sram ?array? that begins at ad dress 0x10. the fourth element would be at address 0x13. clocking figure 4. clock oscillator on-chip circuit the xtalin and xtalout are the clock pins to the microcontroller. the user connects an external oscillator or a crystal to these pins. when using an external crystal, keep pcb traces between the chip leads and crystal as short as possible (less than 2 cm). a 6 mhz fundamental frequency parallel resonant crystal is connected to th ese pins to provide a reference frequency for the internal pll. the two internal 30 pf load caps appear in series to the external crystal and would be equivalent to a 15 pf load. therefore, the crystal must have a required load capacitance of about 15?18 pf. a ceramic resonator does not allow the microcontroller to meet the timing specifications of full speed usb and so a ceramic resonator is not recommended with these parts. an external 6 mhz clock is applied to the xtalin pin if the xtalout pin is left open. grounding the xtalout pin when driving xtalin with an oscillator does not work because the internal clock is effectively shorted to ground. xtalout xtalin to internal pll 30 pf 30 pf (pin 1) (pin 2) [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 15 of 61 reset the cy7c66x13c supports two resets: por and a watchdog reset (wdr). each of these resets causes: all registers to be restored to their default states. the usb device addresses to be set to 0. all interrupts to be disabled. the psp and dsp to be set to memory address 0x00. the occurrence of a reset is recorded in the processor status and control register, as described in processor status and control register on page 27 . bits 4 and 6 are used to record the occurrence of por and wdr, respectively. firmware interrogates these bits to dete rmine the cause of a reset. program execution starts at rom address 0x0000 after a reset. although this looks similar to interrupt vector 0, there is an important difference. reset processing does not push the program counter, carry flag, and zero flag onto program stack. the firmware reset handler should configure the hardware before the ?main? loop of code. attempting to execute a ret or reti in the firmware reset handler causes unpredictable execution results. power on reset when v cc is first applied to the chip, the por signal is asserted and the cy7c66x13c enters a ?s emi-suspend? state. during the semi-suspend state, which is di fferent from the suspend state defined in the usb specificati on, the oscillator and all other blocks of the part are functio nal, except for the cpu. this semi-suspend time ensures that both a valid v cc level is reached and that the internal pll has time to stabilize before full operation begins. when the v cc rises above approximately 2.5 v, and the oscillator is stable, the por is deasserted and the on-chip timer starts counting. the first 1 ms of suspend time is not interruptible, and the semi-suspend state continues for an additional 95 ms unless the count is bypassed by a usb bus reset on the upstream port. the 95 ms provides time for v cc to stabilize at a valid operating vo ltage before the chip executes code. if a usb bus reset occurs on the upstream port during the 95 ms semi-suspend time, the semi-suspend state is aborted and program execution begins immedi ately from address 0x0000. in this case, the bus reset interrupt is pending but not serviced until firmware sets the usb bus reset interrupt enable bit (bit 0 of register 0x20) and enables interrupts with the ei command. the por signal is asserted whenever v cc drops below approximately 2.5 v, and remains asserted until v cc rises above this level again. behavior is the same as described earlier. watchdog reset the wdr occurs when the internal wdt rolls over. writing any value to the write only watchdog restart register at address 0x26 clears the timer. the timer rolls over and wdr occurs if it is not cleared within t watch (8 ms minimum) of the last clear. bit 6 of the processor status and control register is set to record this event (the register contents are set to 010x0001 by the wdr). a wdt reset lasts for 2 ms, after which the microcontroller begins execution at rom address 0x0000. the usb transmitter is disabled by a wdr because the usb device address registers are cleared (see usb device addresses on page 39 ). otherwise, the usb controller responds to all address 0 transactions. it is possible to set the wdr bit of the processor status and control register (0xff) following a por event. if a firmware interrogates the processor status and control register for a set condition on the wdr bit, the wdr bit should be ignored if the por (bit 3 of register 0xff) bit is set. figure 5. watchdog reset last write to wdt register no write to wdt register, so wdr goes high execution begins at reset vector 0x0000 t watch 2 ms [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 16 of 61 suspend mode the cy7c66x13c is placed into a low power state by setting the suspend bit of the processor status and control register. all logic blocks in the device are turned off except the gpio interrupt logic and the usb receiver. the clock oscillator, pll, and the free-running and wdts are shut down. only the occurrence of an enabled gpio interrupt or non idle bus activity at a usb upstream or downstream port wa kes the part from suspend. the run bit in the processor status and control register must be set to resume a part out of suspend. the clock oscillator restarts immediately after exiting suspend mode. the microcontroller returns to a fully functional state 1 ms after the oscillator is stable. the microcontroller executes the instruction following the i/o write that placed the device into suspend mode before servic ing any interrupt requests. the gpio interrupt allows the controller to wake up periodically and poll system components while maintaining a very low average power consumption. to achieve the lowest possible current during suspend mode, all i/o should be held at v cc or gnd. this also applies to internal port pins that may not be bonded in a particular package. typical code for entering suspend is given here: ... ; all gpio set to low power state (no floating pins) ... ; enable gpio interrupts if desired for wakeup mov a, 09h; set suspend and run bits iowr ffh; write to status and control register ? enter suspend, wait for usb activity (or gpio interrupt) nop ; this executes before any isr general purpose i/o (gpio) ports there are up to 31 gpio pins (p0[7:0], p1[7:0], p2[7:0], and p3[6:0]) for the hardware interface. the number of gpio pins chang es based on the package type of the chip. each port is configured as inputs with internal pull ups, open drain outputs, or traditi onal cmos outputs. port 3 offers a higher current dr ive, with typical current sink capability of 12 ma. the data for each gpio port is ac cessible through the data registers. port data registers are shown in table 7 on page 17 through table 10 on page 17 , and are set to 1 on reset. figure 6. block diagram of a gpio pin gpio v cc 14 k ? gpio cfg mode 2-bits data out latch internal data bus port read port write interrupt enable control control interrupt controller q1 q3* q2 *port 0,1,2: low i sink port 3: high i sink data interrupt latch oe reg_bit strb data in latch (latch is transparent except in hapi mode) pin [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 17 of 61 table 7. port 0 data port 0 data address 0x00 table 8. port1 data port 1data address 0x01 table 9. port 2 data port 2 data address 0x02 table 10. port 3 data port 3 data address 0x03 special care should be taken with any unused gpio data bits. an unused gpio data bit, either a pin on the chip or a port bit that is not bonded on a partic ular package, must not be left floating when the device enters the suspend state. if a gpio data bit is left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the usb specifications. if a ?1? is written to the unused data bit and the port is configured with open drain outputs, the unused data bit remains in an indeterminate stat e. therefore, if an unused port bit is programmed in open-drain m ode, it must be written with a ?0.? notice that the cy7c66013c always requires that p3[7:5] be written with a ?0.? when the cy 7c66113c is used the p3[7] should be written with a ?0.? in normal non hapi mode, reads from a gpio port always return the present state of the voltage at the pin, independent of the settings in the port data register s. if hapi mode is activated for a port, reads of that port return latched data as controlled by the hapi signals (see hardware assisted para llel interface (hapi) on page 26 ). during reset, all of the gpio pins are set to a high impedance input state (?1? in open drain mode). writing a ?0? to a gpio pin drives the pin low. in this state, a ?0? is always read on that gpio pin unless an exte rnal source overdrives the internal pull down device. bit #76543210 bit name p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset11111111 bit #76543210 bit name p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset11111111 bit #76543210 bit name p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset11111111 bit #76 5 43210 bit name reserved p3.6 cy7c66113c only p3.5 cy7c66113c only p3.4 p3.3 p3.2 p3.1 p3.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset- 1 1 11111 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 18 of 61 gpio configuration port every gpio port is programmed as inputs with internal pull ups, outputs low or high, or hi-z (flo ating, the pin is not driven i nternally). in addition, the interrupt polarit y for each port is programmed. the port configuration bits ( table 11 ) and the interrupt enable bit ( table 9 on page 17 through table 16 on page 19 ) determine the interrupt polarity of the port pins. table 11. gpio configuration register gpio configuration address 0x08 as shown in ta b l e 1 2 , a positive polarity on an input pin represents a rising edge interrupt (low to high), and a negative polarity on an input pin represents a falling edge interrupt (high to low). the gpio interrupt is generated when all of the following conditions are met: the interrupt enable bit of the associated port interrupt enable register is enab led, the gpio interrupt enable bit of the global interrupt enable register ( table 31 on page 28 ) is enabled, the interrupt enable sense (bit 2, table 30 on page 27 ) is set, and the gpio pin of the port sees an event matching the interrupt polarity. the driving state of each gpio pin is determined by the value written to the pin?s data register ( table 7 on page 17 through table 10 on page 17 ) and by its associated port configuration bits as shown in the gpio configuration register ( table 9 on page 17 ). these ports are configured on a per port basis, so all pins in a given port are config ured together. the possible port configurations are detailed in table 12 . as shown in this table, when a gpio port is configured with cmos outputs, interrupts from that port are disabled. during reset, all the bits in the gpio configuration register are written with ?0? to select hi-z mode for all gpio ports as the default configuration. q1, q2, and q3 discussed here are the transistors referenced in figure 6 on page 16 . the available gpio drive strength are: output low mode: the pin?s data register is set to ?0? writing ?0? to the pin?s data register puts the pin in output low mode, regardless of the contents of the port configuration bits[1:0]. in this mode, q1 and q2 are off. q3 is on. the gpio pin is driven low through q3. output high mode: the pin?s data register is set to 1 and the port configuration bits[1:0] is set to ?10? in this mode, q1 and q3 are off. q2 is on. the gpio is pulled up through q2. the gpio pin is capable of sourcing current. resistive mode: the pin?s data regi ster is set to 1 and the port configuration bits[1:0] is set to ?11? q2 and q3 are off. q1 is on. the gpio pin is pulled up with an internal 14 k ?? resistor. in resistive mode, the pin may serve as an input. reading the pin?s data register returns a logic high if the pin is not driven low by an external source. hi-z mode: the pin?s data register is set to1 and port configuration bits[1:0] is set either ?00? or ?01? q1, q2, and q3 are all off. the gpio pin is not driven internally. in this mode, the pin may serve as an input. reading the port data register returns the actual logic value on the port pins. bit #76543210 bit name port 3 config bit 1 port 3 config bit 0 port 2 config bit 1 port 2 config bit 0 port 1 config bit 1 port 1 config bit 0 port 0 config bit 1 port 0 config bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 table 12. gpio port output control truth table and interrupt polarity port config bit 1 port config bit 0 data register output drive strength interrupt enable bit interrupt polarity 1 1 0 output low 0 disabled 1 resistive 1 ? (falling edge) 1 0 0 output low 0 disabled 1 output high 1 disabled 0 1 0 output low 0 disabled 1 hi-z 1 ? (falling edge) 0 0 0 output low 0 disabled 1 hi-z 1 + (rising edge) [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 19 of 61 gpio interrupt enable ports each gpio pin is individually enabled or disabled as an interru pt source. the port 0?3 interrupt enable registers provide this feature with an interrupt enable bit for each gpio pin. when hapi m ode is enabled the gpio interrupts are blocked, including ports not used by hapi, so gpio pins are not used as interrupt sources. during a reset, gpio interrupts are disabled by clearing all of the gpio interrupt enable ports. writing a ?1? to a gpio interr upt enable bit enables gpio interrupts from the corresponding input pi n. all gpio pins share a common interrupt, as discussed in gpio and hapi interrupt on page 31 . table 13. port 0 interrupt enable port 0 interrupt enable address 0x04 table 14. port 1 interrupt enable port 1 interrupt enable address 0x05 table 15. port 2 interrupt enable port 2 interrupt enable address 0x06 table 16. port 3 interrupt enable port 3 interrupt enable address 0x07 bit #76543210 bit name p0.7 intr enable p0.6 intr enable p0.5 intr enable p0.4 intr enable p0.3 intr enable p0.2 intr enable p0.1 intr enable p0.0 intr enable read/writewwwwwwww reset00000000 bit #76543210 bit name p1.7 intr enable p1.6 intr enable p1.5 intr enable p1.4 intr enable p1.3 intr enable p1.2 intr enable p1.1 intr enable p1.0 intr enable read/writewwwwwwww reset00000000 bit #76543210 bit name p2.7 intr enable p2.6 intr enable p2.5 intr enable p2.4 intr enable p2.3 intr enable p2.2 intr enable p2.1 intr enable p2.0 intr enable read/writewwwwwwww reset00000000 bit #76 5 43210 bit name reserved p3.6 intr enable cy7c66113c only p3.5 intr enable cy7c66113c only p3.4 intr enable p3.3 intr enable p3.2 intr enable p3.1 intr enable p3.0 intr enable read/writeww w wwwww reset00 0 00000 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 20 of 61 dac port the cy7c66113c features a programmable sink current 8-bit port, wh ich is also known as dac port. each of these port i/o pins ha ve a programmable current sink. writing a ?1? to a dac i/o pin disables the output current sink (i sink dac) and drives the i/o pin high through an integrated 14 k ? resistor. when a ?0? is written to a dac i/o pin, the i sink dac is enabled and the pull up resistor is disabled. this causes the i sink dac to sink current to drive the output low. figure 7 shows a block diagram of the dac port pin. the amount of sink current for the dac i/o pin is programmable over 16 values based on the cont ents of the dac isink register ( table 18 on page 21 ) for that output pin. dac[1:0] are high current outputs that are programmable from 3.2 ma to 16 ma (typical). dac[7:2] are low cu rrent outputs, programmable from 0.2 ma to 1.0 ma (typical). when the suspend bit in processor status and control register ( table 30 on page 27 ) is set, the isink dac block of the dac circuitry is disabled. special care should be taken when the cy7c66113c device is placed in the suspend. the dac port data register ( ta b l e 1 7 ) should normally be loaded with all ?1?s ( table 30 on page 27 ) before setting the suspend bit. if any of the dac bits are set to ?0? when the device is suspended, that dac input floats. the floating pin could result in excessive current consumption by the device, unless an external load places the pin in a deterministic state. table 17. dac port data dac port data address 0x30 bit [1..0]: high cu rrent output 3.2 ma to 16 ma typical 1 = i/o pin is an output pulled hgh through the 14 k ? resistor. 0 = i/o pin is an input with an internal 14 k ? pull up resistor. bit [7..2]: low current output 0.2 ma to 1 ma typical 1 = i/o pin is an output pulled hgh through the 14 k ? resistor. 0 = i/o pin is an input with an internal 14 k ? pull up resistor. figure 7. block diagram of a dac pin v cc 14 k ? data out latch internal data bus dac read dac write interrupt enable interrupt logic to interrupt controller q1 internal buffer interrupt polarity isink dac isink register 4 bits dac i/o pin suspend (bit 3 of register 0xff) bit #76543210 bit name dac[7] dac[6] dac[5] da c[4] dac[3] dac[2] dac[1] dac[0] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset11111111 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 21 of 61 dac isink registers each dac i/o pin has an asso ciated dac isink register to program the output sink current when the output is driven low. the fir st isink register (0x38) controls the current for dac[0], the second (0x39) for dac[1], and so on until the isink register at 0x3f , controls the current to dac[7]. table 18. dac sink register dac sink register address 0x38 ?0x3f bit [3..0]: isin k [x] (x= 0..3) writing all ?0?s to the isink register causes 1/5 of the max current to flow through the dac i/o pin. writing all ?1?s to the isink register provides the maximum current flow through the pin. the other 14 states of the dac sink current are evenly spaced between these two values. bit [7..4]: reserved dac port interrupts a dac port interrupt is enabled or disabled for each pin individua lly. the dac port interrupt enable register provides this fea ture with an interrupt enable bit for each dac i/o pin. all of the dac port interrupt enable register bits are cleared to ?0? during a re set. all dac pins share a common interrupt, as explained in dac interrupt on page 31 . table 19. dac port interrupt enable dac port interrupt address 0x31 bit [7..0]: enable bit x (x= 0..7) 1 = enables interrupts from the corresponding bit position; 0 = disables interrupts from the corresponding bit position as an additional benefit, the inte rrupt polarity for each dac pin is programmable with the dac port interrupt polarity register. writing a ?0? to a bit selects negative polarity (falling edge) that causes an interrupt (if enabled) if a falling edge transition occurs on the corresponding input pin. writing a ?1? to a bit in this register selects positive polarity (rising edge) that causes an interrupt (if enabled) if a rising edge transition occurs on the corresponding input pin. all of the dac port inte rrupt polarity register bits are cleared during a reset. table 20. dac port interrupt polarity dac i/o interrupt polarity address 0x32 bit [7..0]: polarity bit x (x= 0..7) 1= selects positive polarity (rising edge) that causes an interrupt (if enabled); 0 = selects negative polarity (falling edge) that causes an interrupt (if enabled). bit #76543210 bit name reserved reserved reserved rese rved isink[3] isink[2] isink[1] isink[0] read/write w w w w reset----0000 bit #76543210 bit name enable bit 7 enable bit 6 enable bit 5 enable bit 4 enable bit 3 enable bit 2 enable bit 1 enable bit 0 read/write w w w w w w w w reset00000000 bit #76543210 bit name polarity bit 7 pol arity bit 6 polarity bit 5 polarity bit 4 polarity bit 3 polarity bit 2 polarity bit 1 polarity bit 0 read/writewwwwwwww reset00000000 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 22 of 61 12-bit free-running timer the 12-bit timer operates with a 1 ? s tick, provides two interrupts (128 ? s and 1.024 ms) and allows the firmware to directly time events that are up to 4 ms in duration. the lower eight bits of the time r is read directly by the firmware. reading the lower 8 bits l atches the upper four bits into a temporary register. when the firmware read s the upper four bits of the time r, it is actually reading the count stored in the temporary register. the effect of this is to ensure a stable 12-bit timer value is read, even when the two reads are sep arated in time. table 21. timer lsb register timer lsb address 0x24 bit [7:0]: timer lower eight bits table 22. timer msb register timer msb address 0x25 bit [3:0]: timer higher nibble bit [7:4]: reserved figure 8. timer block diagram bit #76543210 bit name timer bit 7 timer bit 6 timer bit 5 timer bi t 4 timer bit 3 timer bit 2 timer bit 1 timer bit 0 read/writerrrrrrrr reset00000000 bit #76543210 bit name reserved reserved reserved reserved time r bit 11 timer bit 10 timer bit 9 timer bit 8 read/write - - - - r r r r reset00000000 10 9 7 8 5 6 432 1 mhz clock 1.024 ms interrupt 128 ? s interrupt to timer registers 8 1 0 11 l1 l0 l2 l d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 23 of 61 i 2 c and hapi configuration register internal hardware supports communication with external devices through two interfaces: a two wire i 2 c compatible, and a hapi for 1, 2, or 3 byte transfers. the i 2 c compatible and hapi functions, shar e a common configuration register (see ta b l e 2 3 ) [3] . all bits of this register are cleared on reset. table 23. hapi/i 2 c configuration register i 2 c configuration address 0x09 bits [7,1:0] of the hapi and i 2 c configuration register control the pin out configuration of the hapi and i 2 c compatible interfaces. bits [5:2] are used in hapi mode only, and are described in hardware assisted para llel interface (hapi) on page 26 . ta b l e 2 4 shows the hapi port configurations, and ta b l e 2 5 shows i 2 c pin location configuration options. these i 2 c compatible options exist due to pin limitations in certain packages, and to allow simultaneous hapi and i 2 c compatible operation. hapi operation is enabled whenever either hapi port width bit (bit 1 or 0) is non zero. this affects gpio operation as described in hardware assisted parallel interface (hapi) on page 26 . the i 2 c compatible interface must be separately enabled. i 2 c compatible controller the i 2 c compatible block provides a versatile two wire communication with external devices, supporting master, slave, and multi-master modes of operation. the i 2 c compatible block functions by handling the low level signaling in hardware, and issuing interrupts as needed to allow firmware to take appropriate action during tran sactions. while waiting for firmware response, the hardware keeps the i 2 c compatible bus idle if necessary. the i 2 c compatible interface generates an interrupt to the microcontroller at the end of eac h received or transmitted byte, when a stop bit is detected by the slave when in receive mode, or when arbitration is lost. deta ils of the interrupt responses are given in hardware assisted parallel interface (hapi) on page 26 . the i 2 c compatible interface consists of two registers, an i 2 c data register ( table 14 on page 19 ) and an i 2 c status and control register ( table 27 on page 24 ). the data register is implemented as separate read and write registers. generally, the i 2 c status and control register are only monitored after the i 2 c interrupt, as all bits are valid at that time. polling this register at other times could read misleading bit status if a transaction is underway. the i 2 c scl clock is connected to bit 0 of gpio port 1 or gpio port 2, and the i 2 c sda data is connected to bit 1 of gpio port 1 or gpio port 2. refer to i 2 c and hapi configuration register on page 23 for the bit definitions and functionality of the hapi and i 2 c configuration register, which is used to set the locations of the configurable i 2 c pins. when the i 2 c compatible functionality is enabled by setting bit 0 of the i 2 c status & control register, the two lsb ([1:0]) of the corresp onding gpio port is placed in open drain mode, regardless of the settings of the gpio configuration register. the electr ical characteristics of the i 2 c compatible interface is the same as that of gpio ports 1 and 2. note that the i ol (max) is 2 ma at v ol = 2.0 v for ports 1 and 2. bit #76543210 bit name i 2 c position reserved lempty polarity drdy polarity latch empty data ready hapi port width bit 1 hapi port width bit 0 read/write r/w - r/w r/w r r r/w r/w reset00000000 note 3. i 2 c compatible function must be separately enabled. table 24. hapi port configuration port width (bit 0 and 1, figure 23 ) hapi port width 11 24 bits: p3[7:0], p1[7:0], p0[7:0] 10 16 bits: p1[7:0], p0[7:0] 01 8 bits: p0[7:0] 00 no hapi interface table 25. i 2 c port configuration i 2 c position (bit 7, table 23 on page 23 ) i 2 c port width (bit 1, table 23 on page 23 ) i 2 c position don?t care 1 i 2 c on p2[1:0], 0:scl, 1:sda 00i 2 c on p1[1:0], 0:scl, 1:sda 10i 2 c on p2[1:0], 0:scl, 1:sda [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 24 of 61 all control of the i 2 c clock and data lines is performed by the i 2 c compatible block. table 26. i 2 c data register i 2 c data address 0x29 bits [7..0]: i 2 c data contains 8-bit data on the i 2 c bus. table 27. i 2 c status and control register i 2 c status and control address 0x28 the i 2 c status and control register bits are defined in table 28 , with a more detailed description following. bit #76543210 bit name i 2 c data 7 i 2 c data 6 i 2 c data 5 i 2 c data 4 i 2 c data 3 i 2 c data 2 i 2 c data 1 i 2 c data 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w resetxxxxxxxx bit #76543210 bit name mstr mode continue/bu sy xmit mode ack addr arb lost/restart received stop i 2 c enable read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 table 28. i 2 c status and control register bit definitions bit name description 0i 2 c enable when set to ?1?, the i 2 c compatible function is enabled. when cleared, i 2 c gpio pins operate normally. 1 received stop reads 1 only in slave receive mode, when i 2 c stop bit detected (unless firmware did not ack the last transaction). 2 arb lost/restart reads 1 to indicate master has lost arbitration. reads 0 otherwise. write to 1 in master mode to perform a restart sequence (also set continue bit). 3 addr reads 1 during first byte after start/restart in slave mode, or if master loses arbitration. reads 0 otherwise. this bit should always be written as 0. 4 ack in receive mode, write 1 to generate ack, 0 for no ack. in transmit mode, reads 1 if ack was received, 0 if no ack received. 5 xmit mode write to 1 for transmit mode, 0 for receive mode. 6 continue/busy write 1 to indicate ready for next transaction. reads 1 when i 2 c compatible block is busy with a transaction, 0 when transaction is complete. 7 mstr mode write to 1 for master mode, 0 for slave mode . this bit is cleared if master loses arbitration. clearing from 1 to 0 generates stop bit. [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 25 of 61 bit 7: mstr mode setting this bit to 1 causes the i 2 c compatible block to initiate a master mode transaction by sending a start bit and transmitting the first data byte from the data re gister (this typically holds the target address and r/w bit). subsequent bytes are initiated by setting the continue bit, as described later in this section. clearing this bit (set to 0) c auses the gpio pins to operate normally. in master mode, the i 2 c compatible block generates the clock (sck), and drives th e data line as required depending on transmit or receive state. the i 2 c compatible block performs any required arbitration and clock synchronization. in the event of a loss of arbitration, this mstr bit is cleared, the arb lost bit is set, and an interrupt is generated by the microcontroller. if the chip is the target of an external master that wins arbitration, then the interrupt is held off until th e transaction from the external master is completed. when mstr mode is cleared from 1 to 0 by a firmware write, an i 2 c stop bit is generated. bit 6: continue/busy this bit is written by the firmware to indicate that the firmware is ready for the next byte transaction to begin. in other words, the bit has responded to an interrupt request and has completed the required update or read of the data register. during a read this bit indicates if the hardware is busy and is locking out additional writes to the i 2 c status and control register. this locking allows the hardware to complete certain operations that may require an extended period of time. following an i 2 c interrupt, the i 2 c compatible block does not return to the busy state until firmware sets the continue bit. this allows the firmware to make one control register write without the need to check the busy bit. bit 5: xmit mode this bit is set by firmware to enter transmit mode and perform a data transmit in master or slave mode. clearing this bit sets the part in receive mode. firmware generally determines the value of this bit from the r/w bit associated with the i 2 c address packet. the xmit mode bit state is ignored when initially writing the mstr mode or the restart bits, as these cases always cause transmit mode for the first byte. bit 4: ack this bit is set or cleared by firmware during receive operation to indicate if the hardware shoul d generate an ack signal on the i 2 c compatible bus. writing a 1 to this bit generates an ack (sda low) on the i 2 c compatible bus at the ack bit time. during transmits (xmit mode = 1), this bit should be cleared. bit 3: addr this bit is set by the i 2 c compatible block during the first byte of a slave receive transaction, after an i 2 c start or restart. the addr bit is cleared when the firmware sets the continue bit. this bit allows the firmware to recognize when the master has lost arbitration, and in slave mode it allows the firmware to recognize that a start or restart has occurred. bit 2: arb lost/restart this bit is valid as a status bit (arb lost) after master mode transactions. in master mode, set this bit (along with the continue and mstr mode bits) to perform an i 2 c restart sequence. the i 2 c target address for the restart must be written to the data register before setting the continue bit. to prevent false arb lost signals, the restart bit is cleared by hardware during the restart sequence. bit 1: receive stop this bit is set when the slave is in receive mode and detects a stop bit on the bus. the receive stop bit is not set if the firmware terminates the i 2 c transaction by not acknowledging the previous byte transmitted on the i 2 c compatible bus. for example, in receive mode if firmware sets the continue bit and clears the ack bit. bit 0: i 2 c enable set this bit to override gpio definition with i 2 c compatible function on the two i 2 c compatible pins. when this bit is cleared, these pins are free to function as gpios. in i 2 c compatible mode, the two pins operate in open drain mode, independent of the gpio configuration setting. [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 26 of 61 hardware assisted para llel interface (hapi) the cy7c66x13c processor provides a hardwar e assisted parallel interface for bus widths of 8, 16, or 24 bits, to accommodate da ta transfer with an external microc ontroller or similar device. control bits for selecting the byte width are in the hapi and i 2 c configuration register ( table 23 on page 23 ), bits 1 and 0. signals are provided on port 2 to control the hapi interface. table 29 describes these signals and the hapi control bits in the hapi and i 2 c configuration register. enabling hapi causes the gpio setting in the gpio configuration register ( table 9 on page 17 ) to be overridden. the port 2 output pins are in cmos output mode and port 2 input pins are in input mode (open drain mode with q3 off in figure 6 on page 16 ). hapi read by external device from cy7c66x13c in this case (see figure 14 on page 53 ), firmware writes data to the gpio ports. if 16-bit or 24-b it transfers are being made, port 0 is written last, because writes to port 0 asserts the data ready bit and the dreadypin to signal the external device that data is available. the external device then drives the oe and cs pins active (low), which causes the hapi data to be output on the port pins. when oe is returned high (inactive ), the hapi/gpio interrupt is generated. at that point, firmware is reload the hapi latches for the next output, again writing port 0 last. the data ready bit reads the opposite state from the external dreadypin on pin p2[3]. if the drdy polarity bit is 0, dreadypin is active high, and the data ready bit is active low. hapi write by external device to cy7c66x13c in this case (see figure 16 on page 55 ), the external device drives the stb and cs pins active (low) when it drives new data onto the port pins. when this happens, the internal latches become full, which causes the latch empty bit to be deasserted. when stb is returned high (inactive), the hapi and gpio interrupt is generated. firmware then reads the parallel ports to empty the hapi latches. if 16-bit or 24-bit transfers are being made, port 0 should be read last because reads from port 0 assert the latch empty bit and the latemptypin to signal the external device for more data. the latch empty bit reads the opp osite state from the external latemptypin on pin p2[2]. if the lempty polarity bit is 0, latemptypin is active high, and the latch empty bit is active low. table 29. port 2 pin and hapi configuration bit definitions pin name direction description (port 2 pin) p2[2] latemptypin out ready for more input data from external interface. p2[3] dreadypin out output data r eady for external interface. p2[4] stb in strobe signal for latching incoming data. p2[5] oe in output enable, causes chip to output data. p2[6] cs in chip select (gates stb and oe ). bit name r/w description (hapi and i 2 c configuration register) 2 data ready r asserted after firmware writes data to port 0, until oe driven low. 3 latch empty r asserted after firmware reads data from port 0, until stb driven low. 4 drdy polarity r/w determines polarity of data ready bit and dreadypin: if 0, data ready is active lo w, dreadypin is active high. if 1, data ready is active high, dreadypin is active low. 5 lempty polarity r/w determines polarity of latch empty bit and latemptypin: if 0, latch empty is active low, latemptypin is active high. if 1, latch empty is active high, latemptypin is active low. [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 27 of 61 processor status and control register table 30. processor status and control register processor status and control address 0xff bit 0: run this bit is manipulated by the halt instruction. when halt is executed, all the bits of the processor status and control register are cleared to 0. si nce the run bit is cleared, the processor stops at the end of the current instruction. the processor remains halted until an appropriate reset occurs (power on or watchdog). this bit should normally be written as a ?1.? bit 1: reserved bit 1 is reserved and must be written as a zero. bit 2: interrupt enable sense this bit indicates whether interrupts are enabled or disabled. firmware has no direct control over this bit as writing a zero or one to this bit position has no effect on interrupts. a ?0? indicates that interrupts are masked off and a ?1? indicates that the interrupts are enabled. this bit is further gated with the bit settings of the global interrupt enable register ( table 31 on page 28 ) and usb end point interrupt enable register ( table 32 on page 28 ). instructions di, ei, an d reti manipulate the state of this bit. bit 3: suspend writing a ?1? to the suspend bit halts the processor and cause the microcontroller to enter the su spend mode that significantly reduces power consumption. a pending, enabled interrupt or usb bus activity causes the device to come out of suspend. after coming out of suspend, the device resumes firmware execution at the instruction following th e iowr which put the part into suspend. an iowr attempting to put the part into suspend is ignored if usb bus activity is present. see suspend mode on page 16 for more details on suspend mode operation. bit 4: power on reset the por is set to ?1? during a power on reset. the firmware checks bits 4 and 6 in the reset handler to determine whether a reset was caused by a power on condition or a watchdog timeout. a por event may be followed by a wdr before firmware begins executing, as explained here. bit 5: usb bus reset interrupt the usb bus reset interrupt bit is set when the usb bus reset is detected on receiving a usb bus reset signal on the upstream port. the usb bus reset signal is a single ended zero (se0) that lasts from 12 to 16 ? s. an se0 is defined as the condition in which both the d+ line and the d? line are low at the same time. bit 6: wdr the wdr is set during a reset initiated by the wdt. this indicates the wdt went for more than t watch (8 ms minimum) between watchdog clears. this occurs with a por event. bit 7: irq pending the irq pending, when set, indicates that one or more of the interrupts is recognized as active. an interrupt remains pending until its interrupt enable bit is set ( table 31 on page 28 , table 32 on page 28 ) and interrupts are globally enabled. at that point, the internal interrupt handling sequence clears this bit until another interrupt is detected as pending. during power up, the processor status and control register is set to 00010001, which indicates a por (bit 4 set) has occurred and no interrupts are pending (bit 7 clear). during the 96 ms suspend at start up (explained in power on reset on page 15 ), a wdr also occurs unless this suspend is aborted by an upstream se0 before 8 ms. if a wdr occurs during the power up suspend interval, firmware reads 01010001 from the status and control register after power up. normally, the por bit should be cleared so a subsequent wdr is clearly identified. if an upstream bus reset is received before firmware examines this register, the bus reset bit may also be set. during a wdr, the processor status and control register is set to 01xx0001, which indicates a wdr (bit 6 set) has occurred and no interrupts are pending (bit 7 clear). the wdr does not effect the state of the por and the bus reset interrupt bits. bit #76543210 bit name irq pending watchdog reset usb bus reset interrupt power on reset suspend interrupt enable sense reserved run read/write r r/w r/w r/w r/w r r/w r/w reset00010001 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 28 of 61 interrupts interrupts are generated by the gpio and dac pins, the internal timers, i 2 c compatible or hapi operation, the internal usb hub, or on various usb traffic conditions. all interrupts are maskable by the global interrupt enable register and the usb end point in terrupt enable register. writing a ?1? to a bit position enable s the interrupt associated with that bit position. table 31. global interrupt enable register global interrupt enable register address 0x20 bit 0: usb bus rst interrupt enable 1 = enable interrupt on a usb bus reset; 0 = disable interrupt on a usb bus reset (refer to usb bus reset interrupt on page 30 ). bit 1: 128 ? s interrupt enable 1 = enable timer interrupt every 128 ? s; 0 = disable timer interrupt for every 128 ? s. bit 2: 1.024 ms interrupt enable 1= enable timer interrupt every 1.024 ms; 0 = disable timer interrupt every 1.024 ms. bit 3: usb hub interrupt enable 1 = enable interrupt on a hub status change; 0 = disable interrupt due to hub status change. (refer to usb hub interrupt on page 30 .) bit 4: dac interrupt enable 1 = enable dac interrupt; 0 = disable dac interrupt. bit 5: gpio interrupt enable 1 = enable interrupt on falling and rising edge on any gpio; 0 = disable interrupt on falling and rising edge on any gpio. (refer to sections gpio and hapi interrupt on page 31 , gpio configuration port on page 18 , and gpio interrupt enable ports on page 19 .) bit 6: i 2 c interrupt enable 1 = enable interrupt on i2c related activity; 0 = disable i2c related activity interrupt. (refer to i 2 c interrupt on page 32 .) bit 7: reserved . table 32. usb endpoint interrupt enable register usb endpoint interrupt enable address 0x21 bit 0: epa0 interrupt enable 1 = enable interrupt on data activity through endpoint a0; 0 = disable interrupt on data activity through endpoint a0. bit 1: epa1 interrupt enable 1 = enable interrupt on data activity through endpoint a1; 0 = disable interrupt on data activity through endpoint a1. bit 2: epa2 interrupt enable 1 = enable interrupt on data activity through endpoint a2; 0 = disable interrupt on data activity through endpoint a2. bit 3: epb0 interrupt enable 1 = enable interrupt on data activity through endpoint b0; 0 = disable interrupt on data activity through endpoint b0. bit 4: epb1 interrupt enable 1 = enable interrupt on data activity through endpoint b1; 0 = disable interrupt on data activity through endpoint b1. bit [7..5]: reserved during a reset, the contents the global interrupt enable register and usb end point interrupt enable register are cleared, effectively, disabling all interrupts. the interrupt controller contains a separate flip flop for each interrupt. see figure 9 on page 29 for the logic block diagram of the interrupt controller. when an in terrupt is generated, it is first registered as a pending interrupt. it stays pending until it is serviced or a reset occurs. a pending interrupt only generates an interrupt request if it is enabled by the corresponding bit in the interrupt enable registers. the highest priority interrupt request bit #76543210 bit name reserved i 2 c interrupt enable gpio interrupt enable dac interrupt enable usb hub interrupt enable 1.024 ms interrupt enable 128 ? s interrupt enable usb bus rst interrupt enable read/write - r/w r/w r/w r/w r/w r/w r/w reset- 0000000 bit #76543210 bit name reserved reserved reserved epb1 interrupt enable epb0 interrupt enable epa2 interrupt enable epa1 interrupt enable epa0 interrupt enable read/write - - - r/w r/w r/w r/w r/w reset- - - 00000 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 29 of 61 is serviced following the completion of the currently executing instruction. when servicing an interrupt, the hardware does the following: 1. disables all interrupts by clearing the global interrupt enable bit in the cpu (the state of this bit is read at bit 2 of the processor status and control register, table 30 on page 27 ). 2. clears the flip flop of the current interrupt. 3. generates an automatic call instruction to the rom address associated with the inte rrupt being serviced (that is, the interrupt vector). the instruction in the interrupt t able is typically a jmp instruction to the address of the interrupt service routine (isr). the user re-enables interrupts in the interrupt service routine by executing an ei instruction. interrupts are nested to a level limited only by the available stack space. the program counter value and the carry and zero flags (cf, zf) are stored onto the program stack by the automatic call instruction generated as part of the interrupt acknowledge process. the user firmware is responsible for ensuring that the processor state is preserved and restored during an interrupt. the push a instruction should typically be used as the first command in the isr to save the accumulator value and the pop a instruction should be used to restore the accumulator value just before the reti instruction. the program counter cf and zf are restored and interrupts are enabled when the reti instruction is executed. the di and ei instructions are used to disable and enable interrupts, respectively. these instructions affect only the global interrupt enable bit of the cpu. if desired, ei is used to re-enable interrupts while inside an isr, instead of waiting for the reti that exists the isr. while the global interrupt enable bit is cleared, the presence of a pending interrupt is detected by examining the irq sense bit (bit 7 in the processor status and control register). interrupt vectors the interrupt vectors supported by the usb controller are listed in table 33 on page 30 . the lowest numbered interrupt (usb bus reset interrupt) has the highest priority, and the highest numbered interrupt (i 2 c interrupt) has the lowest priority. figure 9. interrupt controller function diagram clr global interrupt interrupt acknowledge irqout usb reset clear interrupt interrupt priority encoder enable [0] d q 1 enable bit clr usb reset irq 128- ? s clr 128- ? s irq 1-ms clr 1-ms irq addra ep0 irq addra ep0 clr i 2 c irq vector enable [6] clk clr d q clk 1 i 2 c clr i 2 c int usb reset int addra ep1 irq addra ep1 clr irq sense irq controlled by di, ei, and reti instructions dac irq dac clr to cpu cpu gpio/hapi irq gpio/hapi clr hub irq hub clr addra ep2 irq addra ep2 clr addrb ep0 irq addrb ep0 clr addrb ep1 irq addrb ep1 clr (reg 0x20) (reg 0x20) clr enable [2] d q 1 clk addra enp2 int (reg 0x21) int enable sense [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 30 of 61 although reset is not an interrupt, the first instruction exec uted after a reset is at prom address 0x0000h?which corresponds t o the first entry in the interrupt vector table. because the jmp inst ruction is two bytes long, the interrupt vectors occupy two byte s. interrupt latency interrupt latency is calculated from the following equation: interrupt latency = (number of clock cycles remaining in the current instruction) + (10 clock cycles for the call instruction) + (5 clock cycles for the jmp instruction). for example, if a five clock cycle instruction such as jc is being executed when an interrupt occurs, the first instruction of the interrupt service routine exec utes a minimum of 16 clocks (1+10+5) or a maximum of 20 cl ocks (5+10+5) af ter the interrupt is issued. for a 12 mhz internal clock (6 mhz crystal), 20 clock periods is 20/12 mhz = 1.667 ? s. usb bus reset interrupt the usb controller recognizes a usb reset when a single ended zero (se0) condition persists on the upstream usb port for 12?16 ? s. se0 is defined as the condition in which both the d+ line and the d? line are low. a usb bus reset may be recognized for an se0 as short as 12 ? s, but is always recognized for an se0 longer than 16 ? s. when a usb bus reset is detected, bit 5 of the processor status and control register ( table 30 on page 27 ) is set to record this event. in addition, the controller clears the following registers: sie section: usb device address registers (0x10, 0x40) hub section: hub ports connect status (0x48) hub ports enable (0x49) hub ports speed (0x4a) hub ports suspend (0x4d) hub ports resume status (0x4e) hub ports se0 status (0x4f) hub ports data (0x50) hub downstream force (0x51). a usb bus reset interrupt is generated at the end of the usb bus reset condition when the se0 state is deasserted. if the usb reset occurs during the start up delay following a por, the delay is aborted as described in power on reset on page 15 . timer interrupt there are two periodic timer interrupts: the 128 ? s interrupt and the 1.024 ms interrupt. the user should disable both timer interrupts before going into the suspend mode to avoid possible conflicts between servicing the timer interrupts first or the suspend request first. usb endpoint interrupts there are five usb endpoint interrupts, one per endpoint. a usb endpoint interrupt is generated after the usb host writes to a usb endpoint fifo or after th e usb controller sends a packet to the usb host. the interrupt is generated on the last packet of the transaction. for example, on the host?s ack during an in, or on the device ack during on out. if no ack is received during an in transaction, no interrupt is generated. usb hub interrupt a usb hub interrupt is generated by the hardware after a connect/disconnect change, babble, or a resume event is detected by the usb repeater hardware. the babble and resume events are additionally gated by the corresponding bits of the hub port enable register ( table 36 on page 34 ). the connect and disconnect event on a port does not generate an interrupt if the sie does not drive the port (t hat is, the port is being forced). table 33. interrupt vector assignments interrupt vector number rom address function not applicable 0x0000 execution after reset begins here 1 0x0002 usb bus reset interrupt 2 0x0004 128 ? s timer interrupt 3 0x0006 1.024 ms timer interrupt 4 0x0008 usb address a endpoint 0 interrupt 5 0x000a usb address a endpoint 1 interrupt 6 0x000c usb address a endpoint 2 interrupt 7 0x000e usb address b endpoint 0 interrupt 8 0x0010 usb address b endpoint 1 interrupt 9 0x0012 usb hub interrupt 10 0x0014 dac interrupt 11 0x0016 gpio and hapi interrupt 12 0x0018 i 2 c interrupt [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 31 of 61 dac interrupt each dac i/o pin generates an interrupt, if enabled. the interrupt polarity for each dac i/o pin is programmable. a positive polarity is a rising edge input while a negative polarity is a falling edge input. all of the dac pins share a single interrupt vector, which means the firmware needs to read the dac port to determine which pin or pins caused an interrupt. if one dac pin has triggered an interrupt, no other dac pins causes a dac interrupt until that pin has returned to its inactive (non trigger) state or the corresponding interrupt enable bit is cleared. the usb controller does not assign interrupt priority to different dac pins and the dac interrupt enable register is not cleared during the interrupt acknowledge process. gpio and hapi interrupt each of the gpio pins generates an interrupt, if enabled. the interrupt polarity is programmed for each gpio port as part of the gpio configuration. all of the gpio pins share a single interrupt vector, which means the firmware needs to read the gpio ports with enabled interrupts to determine which pin or pins caused an interrupt. a block diagram of the gpio interrupt logic is shown in figure 10 . refer to gpio configuration port on page 18 and gpio interrupt enable ports on page 19 for more informa tion about setting gpio interrupt polarity and enabling individual gpio interrupts. figure 10. gpio interrupt structure if one port pin has triggered an interrupt, no other port pins cause a gpio interrupt until that port pin has returned to its inactive (non trigger) state or its corresponding port interrupt enable bit is cleared. the usb controller does not assign interrupt priority to different port pins and the port interrupt enable registers are not cleared during the interrupt acknowledge process. when hapi is enabled, the hapi logic takes over the interrupt vector and blocks any interrupt from the gpio bits, including ports and bits not used by hapi. operation of the hapi interrupt is independent of the gpio specific bit interrupt enables, and is enabled or disabled only by bit 5 of the global interrupt enable register (0x20) when hapi is enabled. the settings of the gpio bit interrupt enables on ports and bits not used by hapi still effect the cmos mode operation of those ports and bits. the effect of modifying the interrupt bits while the port config bits are set to ?10? is shown in table 12 on page 18 . the events that generate hapi interrupts are described in hardware assisted parallel interface (hapi) on page 26 . port register or gate gpio interrupt flip flop clr gpio pin 1 = enable 0 = disable port interrupt enable register 1 = enable 0 = disable interrupt priority encoder irqout interrupt vector d q m u x 1 (1 input per gpio pin) global gpio interrupt enable (bit 5, register 0x20) ira configuration [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 32 of 61 i 2 c interrupt the i 2 c interrupt occurs after various events on the i 2 c compatible bus to signal the need for firmware interaction. this generally involves reading the i 2 c status and control register ( table 27 on page 24 ) to determine the cause of the interrupt, loading and reading the i 2 c data register as appropriate, and finally writing the processor status and control register ( table 30 on page 27 ) to initiate the subsequent transaction. the interrupt indicates that status bits are stable and it is safe to read and write the i 2 c registers. when enabled, the i 2 c compatible state machines generate interrupts on completion of the following conditions. the referenced bits are in the i 2 c status and control register. in slave receive mode, after the slave receives a byte of data: the addr bit is set, if this is the first byte since a start or restart signal was sent by the external master. firmware must read or write the data register as necessary, then set the ack, xmit mode, and continue/busy bits appropriately for the next byte. in slave receive mode, after a stop bit is detected: the received stop bit is set, if the stop bit follows a slave receive transaction where the ack bit was cleared to 0, no stop bit detection occurs. in slave transmit mode, after the slave transmits a byte of data: the ack bit indicates if the master that requested the byte acknowledged the byte. if more bytes are to be sent, firmware writes the next byte into the data register and then sets the xmit mode and continue/busy bits as required. in master transmit mode, after the master sends a byte of data. firmware should load the data register if necessary, and set the xmit mode, mstr mode , and continue/busy bits appropriately. clearing the mstr mode bit issues a stop signal to the i 2 c compatible bus and return to the idle state. in master receive mode, after the master receives a byte of data: firmware should read the data and set the ack and continue/busy bits appropriately for the next byte. clearing the mstr mode bit at the same time causes the master state machine to issue a stop signal to the i 2 c compatible bus and leave the i 2 c compatible hardware in the idle state. when the master loses arbitration: this condition clears the mstr mode bit and sets the arb lost/restart bit immediately and then waits for a stop signal on the i 2 c compatible bus to generate the interrupt. the continue/busy bit is cleared by hardware prior to interrupt conditions 1 to 4. when the data register is read or written, firmware should configure the other control bits and set the continue/busy bit for subsequent transactions. following an interrupt from master mode, firmware should perform only one write to the status and control register that sets the continue/busy bit, without checking the value of the continue/busy bit. the busy bit may otherwise be active and i 2 c register contents may be changed by the hardware during the transaction, until the i 2 c interrupt occurs. usb overview the usb hardware includes a usb hub repeater with one upstream and four downstream ports. the usb hub repeater interfaces to the microcontroller through a full speed serial interface engine. an external series resistor of r ext must be placed in series with all upst ream and downstream usb outputs to meet the usb driver require ments of the usb specification. the cy7c66x13c microcontroller pr ovides the functionality of a compound device consisting of a usb hub and permanently attached functions. usb serial interface engine the sie allows the cy7c66x13c microcontroller to communicate with the usb hos t through the usb repeater portion of the hub. the sie simp lifies the interface between the microcontroller and usb by incorporating hardware that handles the following usb bus activity independently of the microcontroller: bit stuffing and unstuffing checksum generation and checking ack/nak/stall token type identification address checking. firmware is required to handle the following usb interface tasks: coordinate enumeration by responding to setup packets fill and empty the fifos suspend and resume coordination verify and select data toggle values. usb enumeration the internal hub and any compound device function are enumerated under firmware control. the hub is enumerated first, followed by any integrated compound function. after the hub is enumerated, the usb host reads hub connection status to determine which (if any) of the downstream ports need to be enumerated. the following is a brief summary of the typical enumeration process of the cy7c66x13c by the usb host. for a detailed description of the enumeration process, refer to the usb specification. in this description, ?firmware? refers to embedded firmware in the cy7c66x13c controller. 1. the host computer sends a setup packet followed by a data packet to usb address 0 requesting the device descriptor. 2. firmware decodes the request and retrieves its device descriptor from the program memory tables. 3. the host computer performs a control read sequence and firmware responds by sending the device descriptor over the usb bus, via the on-chip fifos. 4. after receiving the descriptor, the host sends a setup packet followed by a data packet to address 0 assigning a new usb address to the device. [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 33 of 61 5. firmware stores the new address in its usb device address register (for example, as addr ess b) after the no data control sequence completes. 6. the host sends a request for the device descriptor using the new usb address. 7. firmware decodes the request and retrieves the device descriptor from program memory tables. 8. the host performs a control read sequence and firmware responds by sending its device descriptor over the usb bus. 9. the host generates control reads from the device to request the configuration and report descriptors. 10.when the device receives a set configuration request, its functions may now be used. 11.following enumeration as a hub, firmware optionally indicates to the host that a compound device exists (for example, the keyboard in a keyboard/hub device). 12.the host carries out the e numeration process with this additional function as though it were attached downstream from the hub. 13.when the host assigns an address to this device, it is stored as the other usb address (f or example, address a). usb hub a usb hub is required to support: connectivity behavior: service connect and disconnect detection bus fault detection and recovery full and low speed device support. these features are mapped onto a hub repeater and a hub controller. the hub controller is supported by the processor integrated into the cy7c66013c and cy7c66113c microcontrollers. the hardware in the hub repeater detects whether a usb device is connected to a downstream port and the interface speed of the down stream device. the connection to a downstream port is through a differential signal pair (d+ and d?). each downstream port provided by the hub requires external r udn resistors from each signal line to ground, so that when a downstream port has no device connected, the hub reads a low (zero) on both d+ and d?. this condition is used to identify the ?no connect? state. the hub must have a resistor r uup connected between its upstream d+ line and v reg to indicate it is a full speed usb device. the hub generates an eop at eof1, in accordance with the usb 1.1 specificatio n, section 11.2.2. connecting and disconnecting a usb device a low speed (1.5 mbps) usb device has a pull up resistor on the d? pin. at connect time, the bias resistors set the signal levels on the d+ and d? lines. when a low speed device is connected to a hub port, the hub sees a low on d+ and a high on d?. this causes the hub repeater to set a connect bit in the hub ports connect status register for the downstream port. then the hub repeater generates a hub interrupt to notify the microcontroller that there is a change in the hub downstream status. a full speed (12 mbps) usb device has a pull up resistor from the d+ pin, so the hub sees a high on d+ and a low on d?. in this case, the hub repeater sets a connect bit in the hub ports connect status register, clears a bit in the hub ports speed register (for full speed), and generates a hub interrupt to notify the microcontroller of the change in hub status. the firmware sets the speed of this port in the hub ports speed register (see table 35 on page 34 ). connects are recorded by the time a non se0 state lasts for more than 2.5 ? s on a downstream port. when a usb device is disconnected from the hub, the downstream signal pair eventually floats to a single ended zero state. the hub repeater recogn izes a disconnect when the se0 state on a downstream port lasts from 2.0 to 2.5 ? s. on a disconnect, the corresponding bit in the hub ports connect status register is cleared, and the hub interrupt is generated. table 34. hub ports connect status hub ports connect status address 0x48 bit [0..3]: port x connect status (where x = 1..4) when set to 1, port x is connected; when set to 0, port x is disconnected. bit [7..4]: reserved . the hub ports connect status register is cleared to zero by reset or usb bus reset, then set to match the hardware configuration by the hub repeater hardware. the reserved bits [7..4] should always read as ?0? to indicate no connection. bit #76543210 bit name reserved reserved reserved reserved port 4 connect status port 3 connect status port 2 connect status port 1 connect status read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 34 of 61 table 35. hub ports speed hub ports speed address 0x4a bit [0..3]: port x speed (where x = 1..4) set to 1 if the device plugged in to port x is low speed; set to 0 if the device plugged in to port x is full speed. bit [7..4]: reserved. the hub ports speed register is cleared to zero by reset or bus reset. this must be set by the firmware on issuing a port reset. the reserved bits [7..4] should always read as ?0.? enabling and disabling a usb device after a usb device connection is detected, firmware must update status change bits in the hub status change data structure that is polled periodi cally by the usb host. the host responds by sending a packet that instructs the hub to reset and enable the downstream port. firmware then sets the bit in the hub ports enable register, table 36 , for the downstream port. the hub repeater hardware responds to an enable bit in the hub ports enable register by enabli ng the downstream port, so that usb traffic flows to and from that port. if a port is marked enabled and is not suspended, it receives all usb traffic from the upstream port, and usb traffic from the downstream port is passed to the upstream port (unless babble is detected). low speed ports do not receive full speed traffic from the upstream port. when firmware writes to the hub ports enable register to enable a port, the port is not enabled until the end of any packet currently being transmitted. if there is no usb traffic, the port is enabled immediately. when a usb device disconnection is detected, firmware must update status bits in the hub c hange status data structure that is polled periodically by the usb host. in suspend, a connect or disconnect event generates an in terrupt (if the hub interrupt is enabled) even if the port is disabled. table 36. hub ports enable register hub ports enable register address 0x49 bit [0..3]: port x enab le (where x = 1..4) set to 1 if port x is enabled; set to 0 if port x is disabled. bit [7..4]: reserved. the hub ports enable register is cleared to zero by reset or bus reset to disable all downstream po rts as the default condition. a port is also disabled by internal hub hardware (enable bit cleared) if babble is detected on that downstream port. babble is defined as: any non idle downstream traffic on an enabled downstream port at eof2 any downstream port with upstr eam connectivity established at eof2 (that is, no eop received by eof2). bit #76543210 bit name reserved reserved reserved reserved port 4 speed port 3 speed port 2 speed port 1 speed read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit #76543210 bit name reserved reserved reserved reserved port 4 enable port 3 enable port 2 enable port 1 enable read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 35 of 61 hub downstream ports status and control data transfer on hub downstream ports is controlled according to the bit settings of the hub downstream ports control register ( ta b l e 3 7 ). each downstream port is controlled by two bits, as defined in ta b l e 3 8 . the hub downstream ports control register is cleared upon reset or bus reset, and the reset state is the state for normal usb traffic. any downstream port being forced must be marked as disabled ( table 36 on page 34 ) for proper operation of the hub repeater. firmware uses this register for driving bus reset and resume signaling to downstream ports. controlling the port pins through this register uses standard usb edge rate control according to the speed of the port, set in the hub port speed register. the downstream usb ports are designed for connection of usb devices, but also serves as output ports under firmware control. this allows unused usb ports to be used for functions such as driving leds or providing addit ional input signals. pulling up these pins to voltages above v ref may cause current flow into the pin. this register is not reset by bus reset. these bits must be cleared before going into suspend. table 37. hub downstream ports control register hub downstream ports control register address 0x4b an alternate means of forcing the downstream port s is through the hub ports force low register ( table 39 ). with these registers the pins of the downstream ports ar e individually forced low, or left unforced. un like the hub downstream po rts control register, a bove, the force low register does not produce st andard usb edge rate control on the forced pins . however, this register allows downst ream port pins to be held low in suspend. this register is used to drive se0 on all downstream por ts when unconfigured, as required in the usb 1.1 specification. table 39. hub ports force low register hub ports force low address 0x51 the data state of downstream ports are read through the hub ports se0 status register ( table 40 on page 36 ) and the hub ports data register ( table 41 on page 36 ). the data read from the hub ports data regist er is the differential data only and is independent of the settings of the hub ports speed register ( table 35 on page 34 ). when the se0 condition is sensed on a downstream port, the corresponding bits of the hub ports data register hold the last differential data state before the se0. hub ports se0 status re gister and hub ports data register are cleared upon reset or bus reset. bit #76543210 bit name port 4 control bit 1 port 4 control bit 0 port 3 control bit 1 port 3 control bit 0 port 2 control bit 1 port 2 control bit 0 port 1 control bit 1 port 1 control bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 table 38. control bit defini tion for downstream ports control bits control action bit1 bit 0 0 0 not forcing (normal usb function) 0 1 force differential ?1? (d+ high, d? low) 1 0 force differential ?0? (d+ low, d? high) 1 1 force se0 state bit #76543210 bit name force low d+[4] force low d-[4] force low d+[3] force low d?[3] force low d+[2] force low d?[2] force low d+[1] force low d?[1] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 36 of 61 table 40. hub ports se0 status register hub ports se0 status address 0x4f bit [0..3]: port x se0 status (where x = 1..4) set to 1 if a se0 is output on the port x bus; set to 0 if a non-se0 is output on the port x bus. bit [7..4]: reserved. table 41. hub ports data register hub ports data address 0x50 bit [0..3]: port x diff data (where x = 1..4) set to 1 if d+ > d? (forced differ ential 1, if signal is differential, i.e. not a se0 or se1). set to 0 if d? > d+ (for ced differential 0, if signal is differential, i.e., not a se0 or se1); bit [7..4]: reserved. downstream port suspend and resume the hub ports suspend register ( table 42 ) and hub ports resume status register ( table 49 on page 41 ) indicate the suspend and resume conditions on downstream ports. the suspend register must be set by firmware for any ports that are selectively suspended. also, this register is only valid for ports that are selectively suspended. if a port is marked as selectively suspended, normal usb traffic is not sent to that port. resume traffic is also prevented from going to that port, unless the resume comes from the selectively suspended port. if a resume cond ition is detected on the port, hardware reflects a resume ba ck to the port, sets the resume bit in the hub ports resume register, and generates a hub interrupt. if a disconnect occurs on a port marked as selectively suspended, the suspend bit is cleared. the device remote wakeup bit (bit 7) of the hub ports suspend register controls whether or not the resume signal is propagated by the hub after a connect or a disconnect event. if the device remote wakeup bit is set, the hub automatically propagates the resume signal after a connect or a disconnect event. if the device remote wakeup bit is cleared, the hub does not propagate the resume signal. th e setting of the device remote wakeup flag has no impact on the propagation of the resume signal after a downstream remote wakeup event. the hub automatically propagates the resume signal after a remote wakeup event, regardless of t he state of the device remote wakeup bit. the state of this bit has no impact on the generation of the hub interrupt. these regist ers are cleared on reset or usb bus reset. table 42. hub ports suspend register hub ports suspend address 0x4d bit [0..3]: port x selecti ve suspend (where x = 1..4) set to 1 if port x is selectivel y suspended; set to 0 if port x do not suspend. bit 7: device remote wakeup. when set to 1, enable hardware upstream resume signaling for connect and disconnect events during global resume. when set to 0, disable hardware upstream resume signaling for connect and disconnect events during global resume. bit #76543210 bit name reserved reserved reserved reserved port 4 se0 status port 3 se0 status port 2 se0 status port 1 se0 status read/write---- rrrr reset00000000 bit #76543210 bit name reserved reserved reserved reserved port 4 diff. data port 3 diff. data port 2 diff. data port 1 diff. data read/write----rrrr reset00000000 bit #76543210 bit name device remote wakeup reserved reserved reserved port 4 selective suspend port 3 selective suspend port 2 selective suspend port 1 selective suspend read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 37 of 61 table 43. hub ports resume status register hub ports resume address 0x4e bit [0..3]: resume x (where x = 1..4) when set to 1 port x requesting to be resumed (set by hardware); default state is 0; bit [7..4]: reserved . the reserved bits [7..4] should always read as ?0?. resume from a selectively suspended port, with the hub not in suspend, typically involves these actions: 1. hardware detects the resume, drives a k to the port, and generates the hub interrupt. the corresponding bit in the resume status register (0x4e) reads ?1? in this case. 2. firmware responds to hub interrupt, and reads register 0x4e to determine the source of the resume. 3. firmware begins driving k on the port for 10 ms or more through register 0x4b. 4. firmware clears the selective suspend bit for the port (0x4d), which clears the resume bit (0x4e). this ends the hardware driven resume, but the firmware driven resume continues. to prevent traffic being fed by the hub repeater to the port during or just after the resume, firmware should disable this port. 5. firmware drives a timed se0 on the port for two low speed bit times as appropriate. note firmware must disable interrupts during this se0 so the se0 pulse is not inadvertently lengthened and appears as a bus reset to the downstream device. 6. firmware drives a j on the port for one low speed bit time, then it idles the port. 7. firmware re-enables the port. resume when the hub is suspended typically involves these actions: 1. hardware detects the resume, drives a k on the upstream (which is then reflected to all downstream enabled ports), and generates the hub interrupt. 2. the part comes out of susp end and the clocks start. 3. when the clocks are stable, firmware execution resumes. an internal counter ensures that this takes at least 1 ms. firmware should check for re sume from any selectively suspended ports. if found, the selective suspend bit for the port should be cleared; no other action is necessary. 4. the resume ends when the host stops sending k from upstream. firmware should check for changes to the enable and connect registers. if a port has become disabled but is still connected, an se0 is dete cted on the port. the port is treated as being reset, and is reported to the host as newly connected. firmware chooses to clear the device remote wakeup bit (if set) to implement firmware timed states for port changes. all allowed port changes wake the part. then, the part uses internal timing to determine whether to take action or return to suspend. if device remote wakeup is set, automatic hardwa re assertions take place on resume events. bit #76543210 bit name reserved reserved reserved reserved resume 4 resume 3 resume 2 resume 1 read/write---- rrrr reset00000000 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 38 of 61 usb upstream port status and control usb status and control is regulated by the u sb status and control register, as shown in ta b l e 4 4 . all bits in the register are cleared during reset. table 44. usb status and control register usb status and control address 0x1f bits[2..0]: control action set to control action as per ta b l e 4 5 .the three control bits allow the upstream port to be driven manually by firmware. for normal usb operation, all of thes e bits must be cleared. table 45 shows how the control bits affe ct the upstream port. bit 3: bus activity this is a ?sticky? bit that indica tes if any non idle usb event has occurred on the upstream usb port. firmware should check and clear this bit periodically to detect any loss of bus activity. writing a ?0? to the bus activity bit clears it, while writing a ?1? preserves the current value. in other words, the firmware clears the bus activity bit, but only the sie can set it. bits 4 and 5: d? upstream and d+ upstream these bits give the state of each upstream port pin individually: 1 = high, 0 = low. bit 6: endpoint mode this bit used to configure the number of usb endpoints. see usb device endpoints on page 39 for a detailed description. bit 7: endpoint size this bit used to configure the number of usb endpoints. see usb device endpoints on page 39 for a detailed description. the hub generates an eop at eof1 in accordance with the usb 1.1 specification . bit #76543210 bit name endpoint size endpoint mode d+ upstream d? upstream bus activity control action bit 2 control action bit 1 control action bit 0 read/write r/w r/w r r r/w r/w r/w r/w reset00000000 table 45. control bit defi nition for upstream port control bits control action 000 not forcing (sie controls driver) 001 force d+[0] high, d?[0] low 010 force d+[0] low, d?[0] high 011 force se0; d+[0] low, d?[0] low 100 force d+[0] low, d?[0] low 101 force d+[0] hiz, d?[0] low 110 force d+[0] low, d?[0] hiz 111 force d+[0] hiz, d?[0] hiz [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 39 of 61 usb sie operation the cy7c66x13c sie supports operation as a single device or a compound device. this sect ion describes the two device addresses, the configurable endpoints, and the endpoint function. usb device addresses the usb controller provides two usb device address registers: a (addressed at 0x 10)and b (addressed at 0x40). upon reset and under default conditions, device a has three endpoints and device b has two endpoints. the usb device address register contents are cleared during a reset, setting the usb device addresses to zero and disabling these addresses. ta b l e 4 6 shows the format of the usb address registers. table 46. usb device address registers usb device address (device a, b) addresses 0x10(a) and 0x40(b) bits[6..0]: device address firmware writes this bits durin g the usb enumeration process to the non zero address assigned by the usb host. bit 7: device address enable must be set by firmware before the sie responds to usb traffic to the device address. usb device endpoints the cy7c66x13c controller supports up to two addresses and five endpoints for communication with the host. the configuration of these endpoints, and associated fifos, is controlled by bits [7,6] of the usb status and control register (see table 44 on page 38 ). bit 7 controls the size of the endpoints an d bit 6 controls the number of addresses. these configuration options are detailed i n table 47 . endpoint fifos are part of user ram (as shown in data memory organization on page 13 ). when the sie writes data to a fifo, the internal data bus is driven by the sie; not the cpu. th is causes a short delay in the cpu operation. the delay is three clock cycles per byte. for example, an 8-byte data write by the sie to t he fifo generates a delay of 2 ? s (3 cycles/byte * 83.33 ns/cycle * 8 bytes). usb control endpoint mode registers all usb devices are required to have a control endpoint 0 (epa0 and epb0) that is used to initialize and control each usb address. endpoint 0 provides a ccess to the device configuration information and allows generic usb status and control accesses. endpoint 0 is bidirectional to both receive and transmit data. the other endpoints are unidirectional, but selectable by the user as in or out endpoints. the endpoint mode registers are cleared during reset. when usb status and control register bits [6,7] are set to [0,0] or [1,0], the endpoint 0 epa0 and epb0 mode registers use the format shown in table 48 on page 40 . bit #76543210 bit name device address enable device address bit 6 device address bit 5 device address bit 4 device address bit 3 device address bit 2 device address bit 1 device address bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 table 47. memory allocation for endpoints usb status and control register (0x1f) bits [7, 6] [0,0] [1,0] [0,1] [1,1] two usb addresses: a (3 end- points) & b (2 endpoints) two usb addresses: a (3 end- points) &b (2 endpoints) one usb address: a (5 endpoints) one usb address: a (5 endpoints) label start ad- dress size label start ad- dress size label start ad- dress size label start ad- dress size epb1 0xd8 8 epb0 0xa8 8 epa4 0xd8 8 epa3 0xa8 8 epb0 0xe0 8 epb1 0xb0 8 epa3 0xe0 8 epa4 0xb0 8 epa2 0xe8 8 epa0 0xb8 8 epa2 0xe8 8 epa0 0xb8 8 epa1 0xf0 8 epa1 0xc0 32 epa1 0xf0 8 epa1 0xc0 32 epa0 0xf8 8 epa2 0xe0 32 epa0 0xf8 8 epa2 0xe0 32 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 40 of 61 table 48. usb endpoint 0 mode registers usb device endpoint zero mode (a0, b0) addresses 0x12(a0) and 0x42(b0) bits[3..0]: mode these sets the mode which control how the control endpoint responds to traffic. bit 4: ack this bit is set whenever the sie engages in a transaction to the register?s endpoint that completes with an ack packet. bit 5: endpoint 0 out received 1 = token received is an out token. 0 = token received is not an out token. this bit is set by the sie to report the type of token received by the corresponding device address is an out token. the bit must be cleared by firmware as part of the usb processing. bit 6: endpoint 0 in received 1 = token received is an in token. 0 = token received is not an in token. this bit is set by the sie to report the type of token received by the corresponding device address is an in token. the bit must be cleared by firmware as part of the usb processing. bit 7: endpoint 0 setup received 1 = token received is a setup token. 0 = token received is not a setup token. this bit is set on ly by the sie to report the type of token received by the corresponding device address is a setup token. any write to this bit by the cpu clears it (set it to 0). the bit is forced high from the start of the data packet phase of the setup transaction until the start of the ack packet returned by the sie. the cpu should not clear this bit during this interval, and subsequently, until the cpu first does an iord to this endpoint 0 mode register. the bit must be cleared by firmware as part of the usb processing. note in 5-endpoint mode (usb status and control register bits [7,6] are set to [0,1] or [1,1]), r egister 0x42 serves as non control endpoint 3, and has the format for non control endpoints shown in table 49 on page 41 . bits[6:0] of the endpoint 0 mode register are locked from cpu write operations whenever the si e has updated one of these bits, which the sie does only at th e end of the token phase of a transaction (setup... data... ack, out... data... ack, or in... data... ack). the cpu unlocks these bits by doing a subsequent read of this register. only endpoi nt 0 mode registers are locked when updated. the locking mechanism does not apply to the mode registers of other endpoints. because of these hardware locking features, firmware must perform an iord after an iowr to an endpoint 0 register. this verifies that the contents have changed as desired, and that the sie has not updated these values. while the setup bit is set, the cpu cannot write to the endpoint zero fifos. this prevents firmwa re from overwriting an incoming setup transaction before firmware has a chance to read the setup data. refer to table 47 on page 39 for the appropriate endpoint zero memory locations. the mode bits (bits [3:0]) control how the endpoint responds to usb bus traffic. the mode bit encoding is shown in table 38 on page 35 . additional information on the mode bits are found in table 52 on page 45 and table 51 on page 44 . note the sie offers an ?ack out - status in? mode and not an ?ack out - nak in? mode. therefore, if following the status stage of a control write transfer a usb host were to immediately start the next transfer, the new setup packet could override the data payload of the data stage of the previous control write. bit #7 6543210 bit name endpoint 0 setup received endpoint 0 in received endpoint 0 out received ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset0 0000000 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 41 of 61 usb non control endpoint mode registers the format of the non control endpoint mode registers is shown in ta b l e 4 9 . table 49. usb non control endpoint mode registers usb non control device endpoint mode addresses 0x14, 0x16, 0x44 bits[3..0]: mode these sets the mode which control how the control endpoint responds to traffic. the mode bit encoding is shown in table 38 on page 35 . bit 4: ack this bit is set whenever the sie engages in a transaction to the register?s endpoint that completes with an ack packet. bits[6..5]: reserved must be written zero dur ing register writes. bit 7: stall if this stall is set, the sie stalls an out packet if the mode bits are set to ack-in, and the sie stalls an in packet if the mode bits are set to ack-out. for all other modes, the stall bit must be a low. usb endpoint counter registers there are five endpoint counter registers, with identical forma ts for both control and non control endpoints. these registers c ontain byte count information for usb transactions, and bits for data packet status. the format of these registers is shown in table 50 . table 50. usb endpoi nt counter registers usb endpoint counter addresses 0x11, 0x13, 0x15, 0x41, 0x43 bits[5..0]: byte count these counter bits indicate the number of data bytes in a transaction. for in transactions, firmware loads the count with the number of bytes to be tran smitted to the host from the endpoint fifo. valid values are 0 to 32, inclusive. for out or setup transactions, the count is updated by hardware to the number of data bytes received, plus two for the crc bytes. valid values are 2 to 34, inclusive. bit 6: data valid this bit is set on receiving a proper crc when the endpoint fifo buffer is loaded with data during transactions. this bit is used out and setup tokens only. if the crc is not correct, the endpoint interrupt occurs, but data valid is cleared to a zero. bit 7: data 0/1 toggle this bit selects the data packet? s toggle state: 0 for data0, 1 for data1. for in transactions, fi rmware must set this bit to the desired state. for out or setup transactions, the hardware sets this bit to the state of the received data toggle bit. whenever the count updates from a setup or out transaction on endpoint 0, the counter register locks and cannot be written by the cpu. reading the register unlocks it. this prevents firmware from overwriting a status update on incoming setup or out transactions before firmware has a chance to read the data. only endpoint 0 counter register is locked when updated. the locking mechanism does not apply to the count registers of other endpoints. bit #76543210 bit name stall reserved reserved ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 bit #76543210 bit name data 0/1 to g g l e data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset00000000 [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 42 of 61 endpoint mode and count registers update and locking mechanism the contents of the endpoint mode and counter registers are updated, based on the packet flow diagram in figure 11 on page 43 . two time points, update and setup, are shown in the same figure. the following activities occur at each time point: setup: the setup bit of the endpoint 0 mode register is forced high at this time. this bit is forced hi gh by the sie until the end of the data phase of a control write tr ansfer. the setup bit can not be cleared by firmware during this time. the affected mode and counter registers of endpoint 0 are locked from any cpu writes when they are updated. these registers are unlocked by a cpu re ad, only if the read operation occurs after the update. the firmware needs to perform a register read as a part of the en dpoint isr processing to unlock the effected registers. the locking mechanism on mode and counter registers ensures that the firmware recognizes the changes that the sie might have made since the previous i/o read of that register. update: 1. endpoint mode register ? all the bits are updated (except the setup bit of the endpoint 0 mode register). 2. counter registers ? all bits are updated. 3. interrupt ? if an interrupt is to be generated as a result of the transaction, the interrupt flag for the corresponding endpoint is set at this time. for details on what conditions are required to generate an endpoint interrupt, refer to table 52 on page 45 . 4. the contents of the updated endpoint 0 mode and counter registers are locked, except th e setup bit of the endpoint 0 mode register which was locked earlier. [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 43 of 61 figure 11. token and data packet flow diagram a c k 1. in token h o s t d e v i c e s y n c in a d d r c r c 5 e n d p s y n c d a t a 1/0 c r c 16 s y n c data token packet data packet hand shake packet update host to device device to host host to device s y n c in a d d r c r c 5 e n d p token packet host to device s y n c data packet device to host nak/stall update 2. out or setup token without crc error s y n c o u t / set up a d d r c r c 5 e n d p token packet host to device s y n c d a t a 1/0 c r c 16 data data packet host to device setup ack, nak, stal s y n c hand shake packet update device to host 3. out or setup token with crc error s y n c o u t / set up a d d r c r c 5 e n d p token packet host to device s y n c d a t a 1/0 c r c 16 data data packet host to device update only if fifo is written [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 44 of 61 usb mode tables mode this lists the mnemonic given to the different modes that are set in the endpoint mode register by writing to the lower nibble (bits 0..3). the bit settings for different modes are covered in the column marked ?mode bits.? the status in and status out represent the status stage in the in or out transfer involving the control endpoint. mode bits these column lists the encoding for different modes by setting bits[3..0] of the endpoint mode register. this modes represents how the sie responds to different tokens sent by the host to an endpoint. for instance, if the mode bits are set to ?0001? (nak in/out), the sie responds with an ack on receiving a setup token from the host nak on receiving an out token from the host nak on receiving an in token from the host refer to i 2 c compatible controller on page 23 for more information on sie functioning. setup, in, and out these columns shows the sie?s response to the host on receiving a setup, in, and out token depending on the mode set in the endpoint mode register. a ?check? on the out token column, implies that on receiving an out token the sie checks to see whether the out packet is of zero length and has a data toggle (dtog) set to ?1.? if the dtog bit is set and the received out packet has zero length, the out is acked to complete the transaction. if either of this condition is not met the sie responds with a stalll or just ignore the transaction. a ?tx count? entry in the in colu mn implies that the sie transmit the number of bytes specified in the byte count (bits 3..0 of the endpoint count register) to the host in response to the in token received. a ?tx0 byte? entry in the in colu mn implies that the sie transmit a zero length byte packet in response to the in token received from the host. an ?ignore? in any of the columns means that the device does not send any handshake tokens (no ack) to the host. an ?accept? in any of the columns means that the device responds with an ack to a valid setup transaction to the host. comments some mode bits are automat ically changed by the sie in response to certain usb transactions. for example, if the mode bits [3:0] are set to '1111' which is ack in-status out mode as shown in table 47 on page 39 , the sie changes the endpoint mode bits [3:0] to nak in-status out mode (1110) after ack?ing table 51. usb register mode encoding mode mode bits setup in out comments disable 0000 ignore ignore ignore ignore all usb traffic to this endpoint nak in/out 0001 accept nak nak forced from setup on control endpoint, from modes other than 0000 status out only 0010 accept stall check for control endpoints stall in/out 0011 accept stall stall for control endpoints ignore in/out 0100 accept ignore ignore for control endpoints isochronous out 0101 ignore ignore always for isochronous endpoints status in only 0110 accept tx 0 byte stall for control endpoints isochronous in 0111 ignore tx count ignore for isochronous endpoints nak out 1000 ignore ignore nak is set by sie on an ack from mode 1001 (ack out) ack out(stall [4] =0) ack out(stall [4] =1) 1001 1001 ignore ignore ignore ignore ack stall on issuance of an ack this mode is changed by sie to 1000 (nak out) nak out-status in 1010 accept tx 0 byte nak is set by sie on an ack from mode 1011 (ack out-status in) ack out-status in 1011 accept tx 0 byte ack on issuance of an ack this mode is changed by sie to 1010 (nak out ? status in) nak in 1100 ignore nak ignore is set by sie on an ack from mode 1101 (ack in) ack in(stall [4] =0) ack in(stall [4] =1) 1101 1101 ignore ignore tx count stall ignore ignore on issuance of an ack this mode is changed by sie to 1100 (nak in) nak in ? status out 1110 accept nak check is set by sie on an ack from mode 1111 (ack in ? status out) ack in ? status out 1111 accept tx count check on issuance of an ack this mode is changed by sie to 1110 (nak in ? status out) note 4. stall bit is bit 7 of the usb non control device endpoint mode registers. for more information, refer to usb non control endpoint mode registers on page 41 . [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 45 of 61 a valid status stage out token. the firmware needs to update the mode for the sie to respond appropriately. see table 38 on page 35 for more details on what modes are changed by the sie. a disabled endpoint remains disabled until changed by firmware, and all endpoints reset to the disabled mode (0000). firmware normally enables the endpoint mode after a setconfiguration request. any setup packet to an enabled endpoint with mode set to accept setups are changed by the sie to 0001 (naking ins and outs). any mode set to accept a setup sends an ack handshake to a valid setup token. the control endpoint has three status bits for identifying the token type received (setup, in, or out), but the endpoint must be placed in the correct mode to function as such. non control endpoints should not be placed into modes that accept setups. note that most modes that c ontrol transactions involving an ending ack, are changed by the sie to a corresponding mode which naks subsequent packets following the ack. exceptions are modes 1010 and 1110. the response of the sie are summarized as follows: the sie only responds to valid transactions, and ignores invalid ones. the sie generates an interrupt when a valid transaction is completed or when the fifo is corrupted. fifo corruption occurs during an out or setup transaction to a valid internal address, that ends with a invalid crc. an incoming data packet is valid if the count is < endpoint size + 2 (includes crc) and passes all error checking. an in is ignored by an out configured endpoint and visa versa. the in and out pid status is updated at the end of a transaction. the setup pid status is updated at the beginning of the data packet phase. the entire endpoint 0 mode regist er and the count register are locked to cpu writes at the e nd of any transaction to that endpoint in which an ack is transferred. these registers are only unlocked by a cpu read of the register, which should be done by the firmware only after the transaction is complete. this represents about a 1 ? s window in which the cpu is locked from register writes to these usb registers. normally the firmware should perform a register read at the beginning of the endpoint isrs to unlock and get the mode register information. the interlock on the mode and count registers ensures that the firmware recognizes the ch anges that the sie might have made during the previous transacti on. note that the setup bit of the mode register is not locked. this means that before writing to the mode register, firmware must first read the register to make sure that the setup bi t is not set (which indicates a setup was received, while proc essing the current usb request). this read unlocks the register. so care must be taken not to overwrite the regi ster elsewhere. table 52. decode table for table 53 properties of incoming packets changes to the internal register made by the sie on receiving an incoming packet from the host interrupt 3 2 1 0 token count buffer dval dtog dval count setup in out ack 3 2 1 0 response int byte count (bits 0..5, figure 17-4) sie?s response to the host endpoint mode encoding data valid (bit 6, figure 17-4) received token (setup/in/out) data0/1 (bit7 figure 17-4) pid status bits (bit[7..5], figure 17-2) endpoint mode bits changed by the sie the validity of the received data the quality status of the dma buffer the number of received bytes acknowledge phase completed legend: tx: transmit uc : unchanged rx: receive tx0:transmit 0 length packet available for control endpoint only x: don?t care [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 46 of 61 table 53. details of modes fo r differing tra ffic conditions (see table 52 on page 45 for the decode legend) setup (if accepting setups) properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr see table 33 setup <= 10 data valid updates 1 updates 1 uc uc 1 0 0 0 1 ack yes see table 33 setup > 10 junk x updates updates updates 1 uc uc uc no change ignore yes see table 33 setup x junk invalid updates 0 updates 1 uc uc uc no change ignore yes properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr disabled 0 0 0 0 x x uc x uc uc uc uc uc uc uc no change ignore no nak in/out 0 0 0 1 out x uc x uc uc uc uc uc 1 uc no change nak yes 0 0 0 1 in x uc x uc uc uc uc 1 uc uc no change nak yes ignore in/out 0 1 0 0 out x uc x uc uc uc uc uc uc uc no change ignore no 0 1 0 0 in x uc x uc uc uc uc uc uc uc no change ignore no stall in/out 0 0 1 1 out x uc x uc uc uc uc uc 1 uc no change stall yes 0 0 1 1 in x uc x uc uc uc uc 1 uc uc no change stall yes control write properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr normal out/premature status in 1 0 1 1 out <= 10 data valid updates 1 updates uc uc 1 1 1 0 1 0 ack yes 1 0 1 1 out > 10 junk x updates updates updates uc uc 1 uc no change ignore yes 1 0 1 1 out x junk invalid updates 0 updates uc uc 1 uc no change ignore yes 1 0 1 1 in x uc x uc uc uc uc 1 uc 1 no change tx 0 yes nak out/premature status in 1 0 1 0 out <= 10 uc valid uc uc uc uc uc 1 uc no change nak yes 1 0 1 0 out > 10 uc x uc uc uc uc uc uc uc no change ignore no 1 0 1 0 out x uc invalid uc uc uc uc uc uc uc no change ignore no 1 0 1 0 in x uc x uc uc uc uc 1 uc 1 no change tx 0 yes status in/extra out 0 1 1 0 out <= 10 uc valid uc uc uc uc uc 1 uc 0 0 1 1 stall yes 0 1 1 0 out > 10 uc x uc uc uc uc uc uc uc no change ignore no 0 1 1 0 out x uc invalid uc uc uc uc uc uc uc no change ignore no 0 1 1 0 in x uc x uc uc uc uc 1 uc 1 no change tx 0 yes control read properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr normal in/premature status out 1 1 1 1 out 2 uc valid 1 1 updates uc uc 1 1 no change ack yes 1 1 1 1 out 2 uc valid 0 1 updates uc uc 1 uc 0 0 1 1 stall yes 1 1 1 1 out !=2 uc valid updates 1 updates uc uc 1 uc 0 0 1 1 stall yes 1 1 1 1 out > 10 uc x uc uc uc uc uc uc uc no change ignore no 1 1 1 1 out x uc invalid uc uc uc uc uc uc uc no change ignore no 1 1 1 1 in x uc x uc uc uc uc 1 uc 1 1 1 1 0 ack (back) yes [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 47 of 61 nak in/premature status out 1 1 1 0 out 2 uc valid 1 1 updates uc uc 1 1 no change ack yes 1 1 1 0 out 2 uc valid 0 1 updates uc uc 1 uc 0 0 1 1 stall yes 1 1 1 0 out !=2 uc valid updates 1 updates uc uc 1 uc 0 0 1 1 stall yes 1 1 1 0 out > 10 uc x uc uc uc uc uc uc uc no change ignore no 1 1 1 0 out x uc invalid uc uc uc uc uc uc uc no change ignore no 1 1 1 0 in x uc x uc uc uc uc 1 uc uc no change nak yes status out/extra in 0 0 1 0 out 2 uc valid 1 1 updates uc uc 1 1 no change ack yes 0 0 1 0 out 2 uc valid 0 1 updates uc uc 1 uc 0 0 1 1 stall yes 0 0 1 0 out !=2 uc valid updates 1 updates uc uc 1 uc 0 0 1 1 stall yes 0 0 1 0 out > 10 uc x uc uc uc uc uc uc uc no change ignore no 0 0 1 0 out x uc invalid uc uc uc uc 1 uc uc no change ignore no 0 0 1 0 in x uc x uc uc uc uc 1 uc uc 0 0 1 1 stall yes out endpoint properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr normal out/erroneous in 1 0 0 1 out <= 10 data valid updates 1 updates uc uc 1 1 1 0 0 0 ack yes 1 0 0 1 out > 10 junk x updates updates updates uc uc 1 uc no change ignore yes 1 0 0 1 out x junk invalid updates 0 updates uc uc 1 uc no change ignore yes 1 0 0 1 in x uc x uc uc uc uc uc uc uc no change ignore no (stall [4] = 0) 1 0 0 1 in x uc x uc uc uc uc uc uc uc no change stall no (stall [4] = 1) nak out/erroneous in 1 0 0 0 out <= 10 uc valid uc uc uc uc uc 1 uc no change nak yes 1 0 0 0 out > 10 uc x uc uc uc uc uc uc uc no change ignore no 1 0 0 0 out x uc invalid uc uc uc uc uc uc uc no change ignore no 1 0 0 0 in x uc x uc uc uc uc uc uc uc no change ignore no isochronous endpoint (out) 0 1 0 1 out x updates updates updates updates updates uc uc 1 1 no change rx yes 0 1 0 1 in x uc x uc uc uc uc uc uc uc no change ignore no in endpoint properties of incoming packet changes made by sie to internal registers and mode bits mode bits token count buffer dval dtog dval count setup in out ack mode bits response intr normal in/erroneous out 1 1 0 1 out x uc x uc uc uc uc uc uc uc no change ignore no (stall [4] = 0) 1 1 0 1 out x uc x uc uc uc uc uc uc uc no change stall no (stall [4] = 1) 1 1 0 1 in x uc x uc uc uc uc 1 uc 1 1 1 0 0 ack (back) yes nak in/erroneous out 1 1 0 0 out x uc x uc uc uc uc uc uc uc no change ignore no table 53. details of modes fo r differing tra ffic conditions (see table 52 on page 45 for the decode legend) (continued) [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 48 of 61 1 1 0 0 in x uc x uc uc uc uc 1 uc uc no change nak yes isochronous endpoint (in) 0 1 1 1 out x uc x uc uc uc uc uc uc uc no change ignore no 0 1 1 1 in x uc x uc uc uc uc 1 uc uc no change tx yes register summary addr register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write/ both [5, 6, 7] default/ reset [8] gpio configuration ports 0, 1, 2 and 3 0x00 port 0 data p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 bbbbbbbb 11111111 0x01 port 1 data p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 bbbbbbbb 11111111 0x02 port 2 data p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 bbbbbbbb 11111111 0x03 port 3 data reserved p3.6 cy7c66113c only p3.5 cy7c66113c only p3.4 p3.3 p3.2 p3.1 p3.0 bbbbbbbb -1111111 0x04 port 0 interrupt enable p0.7 intr enable p0.6 intr enable p0.5 intr enable p0.4 intr enable p0.3 intr enable p0.2 intr enable p0.1 intr enable p0.0 intr enable wwwwwwww 00000000 0x05 port 1 interrupt enable p1.7 intr enable p1.6 intr enable p1.5 intr enable p1.4 intr enable p1.3 intr enable p1.2 intr enable p1.1 intr enable p1.0 intr enable wwwwwwww 00000000 0x06 port 2 interrupt enable p2.7 intr enable p2.6 intr enable p2.5 intr enable p2.4 intr enable p2.3 intr enable p2.2 intr enable p2.1 intr enable p2.0 intr enable wwwwwwww 00000000 0x07 port 3 interrupt enable reserved p3.6 intr enable cy7c66113c only p3.5 intr enable cy7c66113c only p3.4 intr enable p3.3 intr enable p3.2 intr enable p3.1 intr enable p3.0 intr enable wwwwwwww 00000000 0x08 gpio configuration port 3 config bit 1 port 3 config bit 0 port 2 config bit 1 port 2 config bit 0 port 1 config bit 1 port 1 config bit 0 port 0 config bit 1 port 0 config bit 0 bbbbbbbb 00000000 hapi i 2 c 0x09 hapi/i 2 c configuration i 2 c position reserved lempty polarity drdy polarity latch empty data ready port width bit 1 port width bit 0 b-bbrrbb 00000000 endpoint a0, ai and a2 configuration 0x10 usb device address a device address a enable device address a bit 6 device address a bit 5 device address a bit 4 device address a bit 3 device address a bit 2 device ad- dress a bit 1 device address a bit 0 bbbbbbbb 00000000 endpoint a0, ai and a2 configuration 0x11 ep a0 counter register data 0/1 toggle data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 bbbbbbbb 00000000 0x12 ep a0 mode register endpoint0 setup received endpoint0 in received endpoint0 out received ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 bbbbbbbb 00000000 0x13 ep a1 counter register data 0/1 toggle data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 bbbbbbbb 00000000 0x14 ep a1 mode register stall - - ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 bbbbbbbb 00000000 0x15 ep a2 counter register data 0/1 toggle data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 bbbbbbbb 00000000 0x16 ep a2 mode register stall - - ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 bbbbbbbb 00000000 usb- cs 0x1f usb status and control endpoint size endpoint mode d+ upstream d? upstream bus activity control bit 2 control bit 1 control bit 0 bbrrbbbb -0xx0000 table 53. details of modes fo r differing tra ffic conditions (see table 52 on page 45 for the decode legend) (continued) notes 5. b: read and write. 6. w: write. 7. r: read. 8. x: unknown [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 49 of 61 interrupt 0x20 global interrupt enable reserved i 2 c interrupt enable gpio interrupt enable dac interrupt enable usb hub interrupt enable 1.024-ms interrupt enable 128 ? s interrupt enable usb bus reset in- terrupt en- able -bbbbbbb -0000000 0x21 endpoint interrupt enable reserved reserved reserved epb1 interrupt enable epb0 interrupt enable epa2 interrupt enable epa1 interrupt enable epa0 interrupt enable ---bbbbb ---00000 timer 0x24 timer (lsb) timer bit 7 timer bit 6 timer bit 5 timer bit 4 t imer bit 3 timer bit 2 timer bit 1 timer bit 0 rrrrrrrr 00000000 0x25 timer (msb) reserved reserved reserved reserved timer bit 11 timer bit 10 time bit 9 timer bit 8 ----rrrr ----0000 i 2 c 0x28 i 2 c control and status mstr mode continue/ busy xmit mode ack addr arb lost/ restart received stop i 2 c enable bbbbbbbb 00000000 0x29 i 2 c data i 2 c data 7 i 2 c data 6 i 2 c data 5 i 2 c data 4 i 2 c data 3 i 2 c data 2 i 2 c data 1 i 2 c data 0 bbbbbbbb xxxxxxxx endpoint b0, b1 configuration 0x40 usb device address b device address b enable device address b bit 6 device address b bit 5 device address b bit 4 device address b bit 3 device address b bit 2 device address b bit 1 device address b bit 0 bbbbbbbb 00000000 0x41 ep b0 counter reg- ister data 0/1 toggle data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 bbbbbbbb 00000000 0x42 ep b0 mode register endpoint 0 setup received endpoint 0 in received endpoint 0 out received ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 bbbbbbbb 00000000 0x43 ep b1 counter reg- ister data 0/1 toggle data valid byte count bit 5 byte count bit 4 byte count bit 3 byte count bit 2 byte count bit 1 byte count bit 0 bbbbbbbb 00000000 0x44 ep b1 mode regis- ter stall - - ack mode bit 3 mode bit 2 mode bit 1 mode bit 0 b--bbbbb 00000000 hub port control, status, suspend resume, se0, force low 0x48 hub port connect status reserved reserved reserved reserved port 4 connect status port 3 connect status port 2 connect status port 1 connect status ----bbbb 00000000 0x49 hub port enable reserved reserved reserved reserved port 4 enable port 3 enable port 2 enable port 1 enable ----bbbb 00000000 0x4a hub port speed reserved reserved reserved reserved port 4 speed port 3 speed port 2 speed port 1 speed ----bbbb 00000000 0x4b hub port control (ports 4:1) port 4 control bit 1 port 4 control bit 0 port 3 control bit 1 port 3 control bit 0 port 2 control bit 1 port 2 control bit 0 port 1 control bit 1 port 1 control bit 0 bbbbbbbb 00000000 0x4d hub port suspend device remote wakeup reserved reserved reserved port 4 selective suspend port 3 selective suspend port 2 selective suspend port 1 selective suspend b---bbbb 00000000 0x4e hub port resume status reserved reserved reserved reserved resume 4 resume 3 resume 2 resume 1 ----rrrr 00000000 0x4f hub port se0 status reserved reserved reserved reserved port 4 se0 sta- tus port 3 se0 sta- tus port 2 se0 status port 1 se0 sta- tus ----rrrr 00000000 0x50 hub ports data reserved reserved reserved reserved port 4 diff. data port 3 diff. data port 2 diff. data port 1 diff. data ----rrrr 00000000 0x51 hub port force low (ports 4:1) force low d+[4] force low d?[4] force low d+[3] force low d?[3] force low d+[2] force low d?[2] force low d+[1] force low d?[1] bbbbbbbb 00000000 0xff process status & control irq pending wdr usb bus reset in- terrupt power-on reset suspend interrupt enable sense reserved run rbbbbrbb 00010001 register summary (continued) addr register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write/ both [5, 6, 7] default/ reset [8] [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 50 of 61 sample schematic figure 12. sample schematic xtalo xtali d0? d0+ d1+ d1? d2? d2+ d3? d3+ d4? d4+ vcc vref vpp gnd gnd in gnd out usb-b vbus d- d+ gnd 0.01 ? f 6.000 mhz 22x2(r ext ) vbus vref vref 0.01 ? f 2.2 ? f 2.2 ? f 1.5k shell 10m 4.7 nf 250 vac power management usb-a vbus d? d+ gnd usb-a vbus d? d+ gnd usb-a vbus d? d+ gnd usb-a vbus d? d+ gnd 15k(x8) 22x8(r ext ) optional 3.3v regulator (r uup ) (r udn ) [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 51 of 61 absolute maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................ ............... ?65 c to +150 c ambient temperature with power applied...... 0 c to +70 c supply voltage on v cc relative to v ss .........?0.5 v to +7.0 v dc input voltage .............................. ?0.5 v to +v cc + 0.5 v dc voltage applied to outputs in high z state ................. ................. ?0.5 v to +v cc + 0.5 v power dissipation..................................................... 500 mw static discharge voltage ......................................... > 2000 v latch up current .................................................. > 200 ma max output sink current into port 0, 1, 2, 3, and dac[1:0] pins .............................. 60 ma max output sink current into dac[7:2] pins.............. 10 ma max output source current from port 1, 2, 3, 4 ........ 30 ma notes 9. add 18 ma per driven usb cable (upstream or downstream). this is based on transitions every two full speed bit times on avera ge. 10. power on reset occurs whenever the voltage on v cc is below approximately 2.5 v. electrical characteristics (fosc = 6 mhz; operating temperature = 0 to 70 c, v cc = 4.0 v to 5.25 v) parameter description conditions min max unit general v ref reference voltage 3.3 v 5% 3.15 3.45 v v pp programming voltage (disabled) ?0.4 0.4 v i cc v cc operating current no gpio source current ? 50 ma i sb1 supply current?suspend mode ? 50 ? a i ref vref operating current no usb traffic [9] ?10ma i il input leakage current any pin ? 1 ? a usb interface v di differential input sensit ivity | (d+)?(d?) | 0.2 ? v v cm differential input common mode range 0.8 2.5 v v se single ended receiver threshold 0.8 2.0 v c in transceiver capacitance ? 20 pf i lo hi-z state data line leakage 0 v < v in < 3.3 v ?10 10 ? a r ext external usb series resistor in series with each usb pin 19 21 ? r uup external upstream usb pull up resistor 1.5 k ? 5%, d+ to v reg 1.425 1.575 k ? r udn external downstream pull down resistors 15 k ? 5%, downstream usb pins 14.25 15.75 k ? power-on reset t vccs v cc ramp rate linear ramp 0 v to v cc [10] 0 100 ms usb upstream/downstream port v uoh static output high 15 k ? 5% to gnd 2.8 3.6 v v uol static output low 1.5 k ? 5% to v ref ?0.3 v z o usb driver output impedance including r ext resistor 28 44 ? general purpose i/o (gpio) r up pull up resistance (typical 14 k ?? 8.0 24.0 k ? v ith input threshold voltage all ports, low to high edge 20% 40% v cc v h input hysteresis voltage all ports, high to low edge 2% 8% v cc vol port 0,1,2,3 output low voltage i ol = 3 ma i ol = 8 ma ?0.4 2.0 v v [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 52 of 61 v oh output high voltage i oh = 1.9 ma (all ports 0,1,2,3) 2.4 ? v dac interface r up dac pull up resistance (typical 14 k ?? 8.0 24.0 k ? i sink0(0) dac[7:2] sink current (0) v out = 2.0 v dc 0.1 0.3 ma i sink0(f) dac[7:2] sink current (f) v out = 2.0 v dc 0.5 1.5 ma i sink1(0) dac[1:0] sink current (0) v out = 2.0 v dc 1.6 4.8 ma i sink1(f) dac[1:0] sink current (f) v out = 2.0 v dc 8 24 ma i range programmed isink ratio: max/min v out = 2.0 v dc [11] 46 t ratio tracking ratio dac[1:0] to dac[7:2] v out = 2.0 v [12] 14 22 i sinkdac dac sink current v out = 2.0 v dc 1.6 4.8 ma i lin differential nonlinearity dac port [13] 0.6 lsb electrical characteristics (fosc = 6 mhz; operating temperature = 0 to 70 c, v cc = 4.0 v to 5.25 v) (continued) parameter description conditions min max unit switching characteristics (f osc = 6.0 mhz) parameter description min max unit clock source f osc clock rate 6 0.25% ? mhz t cyc clock period 166.25 167.08 ns t ch clock high time 0.45 t cyc ? ns t cl clock low time 0.45 t cyc ? ns usb full speed signaling [14] t rfs transition rise time 4 20 ns t ffs transition fall time 4 20 ns t rfmfs rise/fall time matching; (t r /t f ) 90 111 % t dratefs full speed date rate 12 0.25% ? mb/s dac interface t sink current sink response time ? 0.8 ? s hapi read cycle timing t rd read pulse width 15 ? ns t oed oe low to data valid [15, 16] ? 40 ns t oez oe high to data high z [16] ? 20 ns t oedr oe low to data_ready deasserted [15, 16] 0 60 ns notes 11. irange: i sinkn (15)/i sinkn (0) for the same pin. 12. t ratio = i sink1 [1:0](n)/i sink 0[7:2](n) for the same n, programmed. 13. i lin measured as largest step size vs. nominal accordi ng to measured full scale and zero programmed values. 14. per table 7-6 of revision 1.1 of usb specification. 15. for 25 pf load. 16. assumes chip select cs is asserted (low). [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 53 of 61 figure 13. clock timing figure 14. usb data signal timing parameter description min max unit hapi write cycle timing t wr write strobe width 15 ? ns t dstb data valid to stb high (data setup time) [16] 5 ? ns t stbz stb high to data high z (data hold time) [16] 15 ? ns t stble stb low to latch_ empty deasserted [15, 16] 0 50 ns timer signals t watch wdt period 8.192 14.336 ms switching characteristics (f osc = 6.0 mhz) clock t cyc t cl t ch 90% 10% 90% 10% d ? d ? t r t r [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 54 of 61 figure 15. hapi read by external interface from usb microcontroller oe (p2.5, input) data (output) stb (p2.4, input) dreadypin (p2.3, output) internal write internal addr port0 d[23:0] t oed t oez t rd t oedr cs (p2.6, input) int (shown for drdy polarity=0) interrupt generated (ready) [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 55 of 61 figure 16. hapi write by external device to usb microcontroller ordering code definitions data (input) lemptypin (p2.2, output) internal read internal addr port0 d[23:0] t stble t wr t stbz t dstb oe (p2.5, input) cs (p2.6, input) stb (p2.4, input) (not empty) (shown for lempty polarity=0) int interrupt generated ordering information ordering code prom size package type operating range cy7c66013c-pvxc 8 kb 48-pin (300-mil) ssop commercial cy7c66113c-pvxc 8 kb 56-pin (300-mil) ssop commercial cy7c66113c-pvxct 8 kb 56-pin (300-mil) ssop commercial CY7C66113C-XC 8 kb die commercial cy7c66113c-ltxc 8 kb 56-pin qfn commercial cy7c66113c-ltxct 8 kb 56-pin qfn commercial x = blank or t (blank = bulk; t = tape and reel) x = temperature grade = c or a (c = commercial grade; a = automotive grade) x = pb-free x = v or t package type: x = p or l p = 48-pin ssop or 56-pin ssop; l = 56-pin qfn part identifier: 7c66x13 = 7c66013 or 7c66113 company id: cy = cypress cy 7c66x13 - x x x x x [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 56 of 61 package diagrams figure 17. 48-pin shrunk small outline package o48 figure 18. 56-pin shrunk small outline package o56 51-85061-*d 51-85062-*d [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 57 of 61 figure 19. 56-qfn 8 8 1.0 mm epad 4.5 5.2 mm 001-53450 *b [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 58 of 61 quad flat package no leads (qfn) package design notes electrical contact of the part to the printed circuit board (pcb) is made by soldering the leads on the bottom surface of the package to the pcb. hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. a copper (cu) fill is to be designed into the pcb as a thermal pad under the package. heat is transferred from the fx1 through the device?s metal paddle on the bottom side of the package. heat from here, is conducted to the pcb at the thermal pad. it is then condu cted from the thermal pad to the pcb inner ground plane by a 5 x 5 array of via. a via is a plated through hole in the pcb with a fini shed diameter of 13 mil. the qfn?s metal die paddle must be soldered to the pcb?s thermal pad. solder mask is placed on the board top side over each via to resist solder flow into the via. the mask on the top side also minimizes outgassing during the solder reflow process. for further information on this pa ckage design plea se refer to the application note surface mount assembly of amkor?s microleadframe (mlf) technology . this application note can be downloaded from amkor?s website from the following url http://www.amkor.com/products/notes_papers/mlf_appnote_ 0902.pdf. the application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc. figure 20 displays a cross sectional area underneath the package. the cross section is of only one via. the thickness of the solder paste template should be 5 mil. it is recommended that ?no clean? type 3 solder paste is used for mounting the part. nitrogen purge is recommended during reflow. figure 21 is a plot of the solder mask pattern. this pad is thermally connected and is not el ectrically connected inside the chip. to minimize emi, this pad should be connected to the ground plane of the circuit board. figure 20. cross section of the area underneath the qfn package figure 21. plot of the solder mask (white area) 0.017? dia solder mask cu fill cu fill pcb material pcb material 0.013? dia via hole for thermally connecting the qfn to the circuit board ground plane. this figure only shows the top three layers of the circuit board: top solder, pcb dielectric, and the ground plane [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 59 of 61 acronyms the following table lists the acro nyms that are used in this document. document conventions units of measure the following table lists all the abbreviations used to measure the psoc devices. numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowerc ase 'h' (for example, '14h' or '3ah'). hexadecimal numbers may also be represented by a '0x' prefix, the c coding convention. binary numbers have an appended lowercase 'b' (for example, 01010100b' or '01000011b'). numbers not indicated by an 'h', 'b', or 0x are decimal. acronym description cpu central processing unit emi electromagnetic interference fifo first in, first out gpio general purpose input/output hapi hardware assisted parallel interface i/o input/output led light-emitting diode lsb least significant bit msb most significant bit pcb printed circuit board pll phase-locked loop por power on reset qfn quad flat no leads prom programmable read only memory ram random access memory sie serial interface engine ssop shrink small-outline package usb universal serial bus symbol unit of measure c degree celsius cm centi meter mm milli meter k ? kilo ohms a micro amperes s micro seconds ma milli amperes ms milli seconds ns nano seconds ? ohms pf pico farad mhz mega hertz vvolts mw milli watts [+] feedback
cy7c66013c, cy7c66113c document number: 38-08024 rev. *g page 60 of 61 document history page document title: cy7c66013c, cy7c66113c full speed usb (12 mbps) peripheral controller with integrated hub document number: 38-08024 rev. ecn no. submission date orig. of change description of change ** 114525 3/27/02 dsg change from spec number: 38-00591 to 38-08024 *a 124768 03/20/03 mon added register bit definition s; added default bit state of each register. corrected the schematic (location of t he pull-up on d+). added register summary. removed information on the avail ability of the part in pdip package. modified ta b l e 5 1 and provided more explanation regarding locking/unlocking mechanism of the mode register. remove d any information regarding the speed detect bit in hub port speed register being set by hardware. *b 417632 see ecn bha updated part number and ordering information. added qfn package drawing and design notes. corrected bit names in fi gures 9-3, 9-4, 9-5, 9-8, 9-9, 9-10, 10-5, 16-1, 18-1, 18-2, 18-3, 18-6, 18-7, 18-9, 18-10. removed hub ports force low register address 0x52. added hapi to interrupt vector number 11 in table 16-1. corrected bit names in section 21.0. corrected units in table 24.0 for r uup , r udn , r ext , and z o. added die diagram and related information. added hapi to gpio interrupt vect or in table 5-1 and figure 16-3 *c 1825466 see ecn tly/pyrs changed title from "cy7c66013, cy7c66113 full speed usb (12 mbps) peripheral controller with integrated hub" to "cy7c66013c, cy7c66113c full speed usb (12 mbps) peripheral controller with integrated hub" changed package description for cy7c66013c and cy7c66113c from -pvc to -pvxc *d 2720540 06/18/09 dpt/aesa added 56 qfn 8x8x1 mm package diagram and ordering information *e 2896318 03/18/10 aesa removed part cy7c66113c-lfxc. updated all package diagrams. *f 3057657 10/13/10 ajha added ?not recommended for new designs? watermark in the pdf. no technical or content updates. *g 3177081 02/18/2011 nxz added ordering code definitions . updated package diagrams . added acronyms and units of measure . updated in new template. [+] feedback
document number: 38-08024 rev. *g revised march 1, 2011 page 61 of 61 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c66013c, cy7c66113c ? cypress semiconductor corporation, 2002-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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